1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 
5 #include <linux/slab.h>
6 #include <linux/device.h>
7 #include <linux/module.h>
8 #include <linux/mfd/syscon.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/platform_device.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/regmap.h>
15 #include <linux/regulator/driver.h>
16 #include <linux/regulator/of_regulator.h>
17 #include <linux/regulator/machine.h>
18 
19 #define LDO_RAMP_UP_UNIT_IN_CYCLES      64 /* 64 cycles per step */
20 #define LDO_RAMP_UP_FREQ_IN_MHZ         24 /* cycle based on 24M OSC */
21 
22 #define LDO_POWER_GATE			0x00
23 #define LDO_FET_FULL_ON			0x1f
24 
25 struct anatop_regulator {
26 	u32 control_reg;
27 	struct regmap *anatop;
28 	int vol_bit_shift;
29 	int vol_bit_width;
30 	u32 delay_reg;
31 	int delay_bit_shift;
32 	int delay_bit_width;
33 	int min_bit_val;
34 	int min_voltage;
35 	int max_voltage;
36 	struct regulator_desc rdesc;
37 	struct regulator_init_data *initdata;
38 	bool bypass;
39 	int sel;
40 };
41 
anatop_regmap_set_voltage_time_sel(struct regulator_dev * reg,unsigned int old_sel,unsigned int new_sel)42 static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
43 	unsigned int old_sel,
44 	unsigned int new_sel)
45 {
46 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
47 	u32 val;
48 	int ret = 0;
49 
50 	/* check whether need to care about LDO ramp up speed */
51 	if (anatop_reg->delay_bit_width && new_sel > old_sel) {
52 		/*
53 		 * the delay for LDO ramp up time is
54 		 * based on the register setting, we need
55 		 * to calculate how many steps LDO need to
56 		 * ramp up, and how much delay needed. (us)
57 		 */
58 		regmap_read(anatop_reg->anatop, anatop_reg->delay_reg, &val);
59 		val = (val >> anatop_reg->delay_bit_shift) &
60 			((1 << anatop_reg->delay_bit_width) - 1);
61 		ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES <<
62 			val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1;
63 	}
64 
65 	return ret;
66 }
67 
anatop_regmap_enable(struct regulator_dev * reg)68 static int anatop_regmap_enable(struct regulator_dev *reg)
69 {
70 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
71 	int sel;
72 
73 	sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel;
74 	return regulator_set_voltage_sel_regmap(reg, sel);
75 }
76 
anatop_regmap_disable(struct regulator_dev * reg)77 static int anatop_regmap_disable(struct regulator_dev *reg)
78 {
79 	return regulator_set_voltage_sel_regmap(reg, LDO_POWER_GATE);
80 }
81 
anatop_regmap_is_enabled(struct regulator_dev * reg)82 static int anatop_regmap_is_enabled(struct regulator_dev *reg)
83 {
84 	return regulator_get_voltage_sel_regmap(reg) != LDO_POWER_GATE;
85 }
86 
anatop_regmap_core_set_voltage_sel(struct regulator_dev * reg,unsigned selector)87 static int anatop_regmap_core_set_voltage_sel(struct regulator_dev *reg,
88 					      unsigned selector)
89 {
90 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
91 	int ret;
92 
93 	if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) {
94 		anatop_reg->sel = selector;
95 		return 0;
96 	}
97 
98 	ret = regulator_set_voltage_sel_regmap(reg, selector);
99 	if (!ret)
100 		anatop_reg->sel = selector;
101 	return ret;
102 }
103 
anatop_regmap_core_get_voltage_sel(struct regulator_dev * reg)104 static int anatop_regmap_core_get_voltage_sel(struct regulator_dev *reg)
105 {
106 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
107 
108 	if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg))
109 		return anatop_reg->sel;
110 
111 	return regulator_get_voltage_sel_regmap(reg);
112 }
113 
anatop_regmap_get_bypass(struct regulator_dev * reg,bool * enable)114 static int anatop_regmap_get_bypass(struct regulator_dev *reg, bool *enable)
115 {
116 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
117 	int sel;
118 
119 	sel = regulator_get_voltage_sel_regmap(reg);
120 	if (sel == LDO_FET_FULL_ON)
121 		WARN_ON(!anatop_reg->bypass);
122 	else if (sel != LDO_POWER_GATE)
123 		WARN_ON(anatop_reg->bypass);
124 
125 	*enable = anatop_reg->bypass;
126 	return 0;
127 }
128 
anatop_regmap_set_bypass(struct regulator_dev * reg,bool enable)129 static int anatop_regmap_set_bypass(struct regulator_dev *reg, bool enable)
130 {
131 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
132 	int sel;
133 
134 	if (enable == anatop_reg->bypass)
135 		return 0;
136 
137 	sel = enable ? LDO_FET_FULL_ON : anatop_reg->sel;
138 	anatop_reg->bypass = enable;
139 
140 	return regulator_set_voltage_sel_regmap(reg, sel);
141 }
142 
143 static struct regulator_ops anatop_rops = {
144 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
145 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
146 	.list_voltage = regulator_list_voltage_linear,
147 	.map_voltage = regulator_map_voltage_linear,
148 };
149 
150 static struct regulator_ops anatop_core_rops = {
151 	.enable = anatop_regmap_enable,
152 	.disable = anatop_regmap_disable,
153 	.is_enabled = anatop_regmap_is_enabled,
154 	.set_voltage_sel = anatop_regmap_core_set_voltage_sel,
155 	.set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
156 	.get_voltage_sel = anatop_regmap_core_get_voltage_sel,
157 	.list_voltage = regulator_list_voltage_linear,
158 	.map_voltage = regulator_map_voltage_linear,
159 	.get_bypass = anatop_regmap_get_bypass,
160 	.set_bypass = anatop_regmap_set_bypass,
161 };
162 
anatop_regulator_probe(struct platform_device * pdev)163 static int anatop_regulator_probe(struct platform_device *pdev)
164 {
165 	struct device *dev = &pdev->dev;
166 	struct device_node *np = dev->of_node;
167 	struct device_node *anatop_np;
168 	struct regulator_desc *rdesc;
169 	struct regulator_dev *rdev;
170 	struct anatop_regulator *sreg;
171 	struct regulator_init_data *initdata;
172 	struct regulator_config config = { };
173 	int ret = 0;
174 	u32 val;
175 
176 	sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
177 	if (!sreg)
178 		return -ENOMEM;
179 
180 	rdesc = &sreg->rdesc;
181 	rdesc->type = REGULATOR_VOLTAGE;
182 	rdesc->owner = THIS_MODULE;
183 
184 	of_property_read_string(np, "regulator-name", &rdesc->name);
185 	if (!rdesc->name) {
186 		dev_err(dev, "failed to get a regulator-name\n");
187 		return -EINVAL;
188 	}
189 
190 	initdata = of_get_regulator_init_data(dev, np, rdesc);
191 	if (!initdata)
192 		return -ENOMEM;
193 
194 	initdata->supply_regulator = "vin";
195 	sreg->initdata = initdata;
196 
197 	anatop_np = of_get_parent(np);
198 	if (!anatop_np)
199 		return -ENODEV;
200 	sreg->anatop = syscon_node_to_regmap(anatop_np);
201 	of_node_put(anatop_np);
202 	if (IS_ERR(sreg->anatop))
203 		return PTR_ERR(sreg->anatop);
204 
205 	ret = of_property_read_u32(np, "anatop-reg-offset",
206 				   &sreg->control_reg);
207 	if (ret) {
208 		dev_err(dev, "no anatop-reg-offset property set\n");
209 		return ret;
210 	}
211 	ret = of_property_read_u32(np, "anatop-vol-bit-width",
212 				   &sreg->vol_bit_width);
213 	if (ret) {
214 		dev_err(dev, "no anatop-vol-bit-width property set\n");
215 		return ret;
216 	}
217 	ret = of_property_read_u32(np, "anatop-vol-bit-shift",
218 				   &sreg->vol_bit_shift);
219 	if (ret) {
220 		dev_err(dev, "no anatop-vol-bit-shift property set\n");
221 		return ret;
222 	}
223 	ret = of_property_read_u32(np, "anatop-min-bit-val",
224 				   &sreg->min_bit_val);
225 	if (ret) {
226 		dev_err(dev, "no anatop-min-bit-val property set\n");
227 		return ret;
228 	}
229 	ret = of_property_read_u32(np, "anatop-min-voltage",
230 				   &sreg->min_voltage);
231 	if (ret) {
232 		dev_err(dev, "no anatop-min-voltage property set\n");
233 		return ret;
234 	}
235 	ret = of_property_read_u32(np, "anatop-max-voltage",
236 				   &sreg->max_voltage);
237 	if (ret) {
238 		dev_err(dev, "no anatop-max-voltage property set\n");
239 		return ret;
240 	}
241 
242 	/* read LDO ramp up setting, only for core reg */
243 	of_property_read_u32(np, "anatop-delay-reg-offset",
244 			     &sreg->delay_reg);
245 	of_property_read_u32(np, "anatop-delay-bit-width",
246 			     &sreg->delay_bit_width);
247 	of_property_read_u32(np, "anatop-delay-bit-shift",
248 			     &sreg->delay_bit_shift);
249 
250 	rdesc->n_voltages = (sreg->max_voltage - sreg->min_voltage) / 25000 + 1
251 			    + sreg->min_bit_val;
252 	rdesc->min_uV = sreg->min_voltage;
253 	rdesc->uV_step = 25000;
254 	rdesc->linear_min_sel = sreg->min_bit_val;
255 	rdesc->vsel_reg = sreg->control_reg;
256 	rdesc->vsel_mask = ((1 << sreg->vol_bit_width) - 1) <<
257 			   sreg->vol_bit_shift;
258 	rdesc->min_dropout_uV = 125000;
259 
260 	config.dev = &pdev->dev;
261 	config.init_data = initdata;
262 	config.driver_data = sreg;
263 	config.of_node = pdev->dev.of_node;
264 	config.regmap = sreg->anatop;
265 
266 	/* Only core regulators have the ramp up delay configuration. */
267 	if (sreg->control_reg && sreg->delay_bit_width) {
268 		rdesc->ops = &anatop_core_rops;
269 
270 		ret = regmap_read(config.regmap, rdesc->vsel_reg, &val);
271 		if (ret) {
272 			dev_err(dev, "failed to read initial state\n");
273 			return ret;
274 		}
275 
276 		sreg->sel = (val & rdesc->vsel_mask) >> sreg->vol_bit_shift;
277 		if (sreg->sel == LDO_FET_FULL_ON) {
278 			sreg->sel = 0;
279 			sreg->bypass = true;
280 		}
281 
282 		/*
283 		 * In case vddpu was disabled by the bootloader, we need to set
284 		 * a sane default until imx6-cpufreq was probed and changes the
285 		 * voltage to the correct value. In this case we set 1.25V.
286 		 */
287 		if (!sreg->sel && !strcmp(rdesc->name, "vddpu"))
288 			sreg->sel = 22;
289 
290 		/* set the default voltage of the pcie phy to be 1.100v */
291 		if (!sreg->sel && !strcmp(rdesc->name, "vddpcie"))
292 			sreg->sel = 0x10;
293 
294 		if (!sreg->bypass && !sreg->sel) {
295 			dev_err(&pdev->dev, "Failed to read a valid default voltage selector.\n");
296 			return -EINVAL;
297 		}
298 	} else {
299 		u32 enable_bit;
300 
301 		rdesc->ops = &anatop_rops;
302 
303 		if (!of_property_read_u32(np, "anatop-enable-bit",
304 					  &enable_bit)) {
305 			anatop_rops.enable  = regulator_enable_regmap;
306 			anatop_rops.disable = regulator_disable_regmap;
307 			anatop_rops.is_enabled = regulator_is_enabled_regmap;
308 
309 			rdesc->enable_reg = sreg->control_reg;
310 			rdesc->enable_mask = BIT(enable_bit);
311 		}
312 	}
313 
314 	/* register regulator */
315 	rdev = devm_regulator_register(dev, rdesc, &config);
316 	if (IS_ERR(rdev)) {
317 		dev_err(dev, "failed to register %s\n",
318 			rdesc->name);
319 		return PTR_ERR(rdev);
320 	}
321 
322 	platform_set_drvdata(pdev, rdev);
323 
324 	return 0;
325 }
326 
327 static const struct of_device_id of_anatop_regulator_match_tbl[] = {
328 	{ .compatible = "fsl,anatop-regulator", },
329 	{ /* end */ }
330 };
331 MODULE_DEVICE_TABLE(of, of_anatop_regulator_match_tbl);
332 
333 static struct platform_driver anatop_regulator_driver = {
334 	.driver = {
335 		.name	= "anatop_regulator",
336 		.of_match_table = of_anatop_regulator_match_tbl,
337 	},
338 	.probe	= anatop_regulator_probe,
339 };
340 
anatop_regulator_init(void)341 static int __init anatop_regulator_init(void)
342 {
343 	return platform_driver_register(&anatop_regulator_driver);
344 }
345 postcore_initcall(anatop_regulator_init);
346 
anatop_regulator_exit(void)347 static void __exit anatop_regulator_exit(void)
348 {
349 	platform_driver_unregister(&anatop_regulator_driver);
350 }
351 module_exit(anatop_regulator_exit);
352 
353 MODULE_AUTHOR("Nancy Chen <Nancy.Chen@freescale.com>");
354 MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>");
355 MODULE_DESCRIPTION("ANATOP Regulator driver");
356 MODULE_LICENSE("GPL v2");
357 MODULE_ALIAS("platform:anatop_regulator");
358