1 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12 #include <linux/of.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/rtc.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <linux/spinlock.h>
21
22 /* RTC Register offsets from RTC CTRL REG */
23 #define PM8XXX_ALARM_CTRL_OFFSET 0x01
24 #define PM8XXX_RTC_WRITE_OFFSET 0x02
25 #define PM8XXX_RTC_READ_OFFSET 0x06
26 #define PM8XXX_ALARM_RW_OFFSET 0x0A
27
28 /* RTC_CTRL register bit fields */
29 #define PM8xxx_RTC_ENABLE BIT(7)
30 #define PM8xxx_RTC_ALARM_CLEAR BIT(0)
31
32 #define NUM_8_BIT_RTC_REGS 0x4
33
34 /**
35 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
36 * @ctrl: base address of control register
37 * @write: base address of write register
38 * @read: base address of read register
39 * @alarm_ctrl: base address of alarm control register
40 * @alarm_ctrl2: base address of alarm control2 register
41 * @alarm_rw: base address of alarm read-write register
42 * @alarm_en: alarm enable mask
43 */
44 struct pm8xxx_rtc_regs {
45 unsigned int ctrl;
46 unsigned int write;
47 unsigned int read;
48 unsigned int alarm_ctrl;
49 unsigned int alarm_ctrl2;
50 unsigned int alarm_rw;
51 unsigned int alarm_en;
52 };
53
54 /**
55 * struct pm8xxx_rtc - rtc driver internal structure
56 * @rtc: rtc device for this driver.
57 * @regmap: regmap used to access RTC registers
58 * @allow_set_time: indicates whether writing to the RTC is allowed
59 * @rtc_alarm_irq: rtc alarm irq number.
60 * @ctrl_reg: rtc control register.
61 * @rtc_dev: device structure.
62 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
63 */
64 struct pm8xxx_rtc {
65 struct rtc_device *rtc;
66 struct regmap *regmap;
67 bool allow_set_time;
68 int rtc_alarm_irq;
69 const struct pm8xxx_rtc_regs *regs;
70 struct device *rtc_dev;
71 spinlock_t ctrl_reg_lock;
72 };
73
74 /*
75 * Steps to write the RTC registers.
76 * 1. Disable alarm if enabled.
77 * 2. Disable rtc if enabled.
78 * 3. Write 0x00 to LSB.
79 * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
80 * 5. Enable rtc if disabled in step 2.
81 * 6. Enable alarm if disabled in step 1.
82 */
pm8xxx_rtc_set_time(struct device * dev,struct rtc_time * tm)83 static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
84 {
85 int rc, i;
86 unsigned long secs, irq_flags;
87 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
88 unsigned int ctrl_reg, rtc_ctrl_reg;
89 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
90 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
91
92 if (!rtc_dd->allow_set_time)
93 return -EACCES;
94
95 rtc_tm_to_time(tm, &secs);
96
97 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
98
99 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
100 value[i] = secs & 0xFF;
101 secs >>= 8;
102 }
103
104 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
105
106 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
107 if (rc)
108 goto rtc_rw_fail;
109
110 if (ctrl_reg & regs->alarm_en) {
111 alarm_enabled = 1;
112 ctrl_reg &= ~regs->alarm_en;
113 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
114 if (rc) {
115 dev_err(dev, "Write to RTC Alarm control register failed\n");
116 goto rtc_rw_fail;
117 }
118 }
119
120 /* Disable RTC H/w before writing on RTC register */
121 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
122 if (rc)
123 goto rtc_rw_fail;
124
125 if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
126 rtc_disabled = 1;
127 rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
128 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
129 if (rc) {
130 dev_err(dev, "Write to RTC control register failed\n");
131 goto rtc_rw_fail;
132 }
133 }
134
135 /* Write 0 to Byte[0] */
136 rc = regmap_write(rtc_dd->regmap, regs->write, 0);
137 if (rc) {
138 dev_err(dev, "Write to RTC write data register failed\n");
139 goto rtc_rw_fail;
140 }
141
142 /* Write Byte[1], Byte[2], Byte[3] */
143 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
144 &value[1], sizeof(value) - 1);
145 if (rc) {
146 dev_err(dev, "Write to RTC write data register failed\n");
147 goto rtc_rw_fail;
148 }
149
150 /* Write Byte[0] */
151 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
152 if (rc) {
153 dev_err(dev, "Write to RTC write data register failed\n");
154 goto rtc_rw_fail;
155 }
156
157 /* Enable RTC H/w after writing on RTC register */
158 if (rtc_disabled) {
159 rtc_ctrl_reg |= PM8xxx_RTC_ENABLE;
160 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
161 if (rc) {
162 dev_err(dev, "Write to RTC control register failed\n");
163 goto rtc_rw_fail;
164 }
165 }
166
167 if (alarm_enabled) {
168 ctrl_reg |= regs->alarm_en;
169 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
170 if (rc) {
171 dev_err(dev, "Write to RTC Alarm control register failed\n");
172 goto rtc_rw_fail;
173 }
174 }
175
176 rtc_rw_fail:
177 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
178
179 return rc;
180 }
181
pm8xxx_rtc_read_time(struct device * dev,struct rtc_time * tm)182 static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
183 {
184 int rc;
185 u8 value[NUM_8_BIT_RTC_REGS];
186 unsigned long secs;
187 unsigned int reg;
188 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
189 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
190
191 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
192 if (rc) {
193 dev_err(dev, "RTC read data register failed\n");
194 return rc;
195 }
196
197 /*
198 * Read the LSB again and check if there has been a carry over.
199 * If there is, redo the read operation.
200 */
201 rc = regmap_read(rtc_dd->regmap, regs->read, ®);
202 if (rc < 0) {
203 dev_err(dev, "RTC read data register failed\n");
204 return rc;
205 }
206
207 if (unlikely(reg < value[0])) {
208 rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
209 value, sizeof(value));
210 if (rc) {
211 dev_err(dev, "RTC read data register failed\n");
212 return rc;
213 }
214 }
215
216 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
217 ((unsigned long)value[3] << 24);
218
219 rtc_time_to_tm(secs, tm);
220
221 dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n",
222 secs, tm->tm_hour, tm->tm_min, tm->tm_sec,
223 tm->tm_mday, tm->tm_mon, tm->tm_year);
224
225 return 0;
226 }
227
pm8xxx_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alarm)228 static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
229 {
230 int rc, i;
231 u8 value[NUM_8_BIT_RTC_REGS];
232 unsigned long secs, irq_flags;
233 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
234 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
235
236 rtc_tm_to_time(&alarm->time, &secs);
237
238 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
239 value[i] = secs & 0xFF;
240 secs >>= 8;
241 }
242
243 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
244 regs->alarm_en, 0);
245 if (rc)
246 return rc;
247
248 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
249
250 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
251 sizeof(value));
252 if (rc) {
253 dev_err(dev, "Write to RTC ALARM register failed\n");
254 goto rtc_rw_fail;
255 }
256
257 if (alarm->enabled) {
258 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
259 regs->alarm_en, regs->alarm_en);
260 if (rc)
261 goto rtc_rw_fail;
262 }
263
264 dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
265 alarm->time.tm_hour, alarm->time.tm_min,
266 alarm->time.tm_sec, alarm->time.tm_mday,
267 alarm->time.tm_mon, alarm->time.tm_year);
268 rtc_rw_fail:
269 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
270 return rc;
271 }
272
pm8xxx_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alarm)273 static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
274 {
275 int rc;
276 u8 value[NUM_8_BIT_RTC_REGS];
277 unsigned long secs;
278 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
279 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
280
281 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
282 sizeof(value));
283 if (rc) {
284 dev_err(dev, "RTC alarm time read failed\n");
285 return rc;
286 }
287
288 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
289 ((unsigned long)value[3] << 24);
290
291 rtc_time_to_tm(secs, &alarm->time);
292
293 rc = rtc_valid_tm(&alarm->time);
294 if (rc < 0) {
295 dev_err(dev, "Invalid alarm time read from RTC\n");
296 return rc;
297 }
298
299 dev_dbg(dev, "Alarm set for - h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
300 alarm->time.tm_hour, alarm->time.tm_min,
301 alarm->time.tm_sec, alarm->time.tm_mday,
302 alarm->time.tm_mon, alarm->time.tm_year);
303
304 return 0;
305 }
306
pm8xxx_rtc_alarm_irq_enable(struct device * dev,unsigned int enable)307 static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
308 {
309 int rc;
310 unsigned long irq_flags;
311 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
312 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
313 unsigned int ctrl_reg;
314
315 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
316
317 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
318 if (rc)
319 goto rtc_rw_fail;
320
321 if (enable)
322 ctrl_reg |= regs->alarm_en;
323 else
324 ctrl_reg &= ~regs->alarm_en;
325
326 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
327 if (rc) {
328 dev_err(dev, "Write to RTC control register failed\n");
329 goto rtc_rw_fail;
330 }
331
332 rtc_rw_fail:
333 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
334 return rc;
335 }
336
337 static const struct rtc_class_ops pm8xxx_rtc_ops = {
338 .read_time = pm8xxx_rtc_read_time,
339 .set_time = pm8xxx_rtc_set_time,
340 .set_alarm = pm8xxx_rtc_set_alarm,
341 .read_alarm = pm8xxx_rtc_read_alarm,
342 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
343 };
344
pm8xxx_alarm_trigger(int irq,void * dev_id)345 static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
346 {
347 struct pm8xxx_rtc *rtc_dd = dev_id;
348 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
349 unsigned int ctrl_reg;
350 int rc;
351 unsigned long irq_flags;
352
353 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
354
355 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
356
357 /* Clear the alarm enable bit */
358 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
359 if (rc) {
360 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
361 goto rtc_alarm_handled;
362 }
363
364 ctrl_reg &= ~regs->alarm_en;
365
366 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
367 if (rc) {
368 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
369 dev_err(rtc_dd->rtc_dev,
370 "Write to alarm control register failed\n");
371 goto rtc_alarm_handled;
372 }
373
374 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
375
376 /* Clear RTC alarm register */
377 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
378 if (rc) {
379 dev_err(rtc_dd->rtc_dev,
380 "RTC Alarm control2 register read failed\n");
381 goto rtc_alarm_handled;
382 }
383
384 ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
385 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
386 if (rc)
387 dev_err(rtc_dd->rtc_dev,
388 "Write to RTC Alarm control2 register failed\n");
389
390 rtc_alarm_handled:
391 return IRQ_HANDLED;
392 }
393
pm8xxx_rtc_enable(struct pm8xxx_rtc * rtc_dd)394 static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
395 {
396 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
397 unsigned int ctrl_reg;
398 int rc;
399
400 /* Check if the RTC is on, else turn it on */
401 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
402 if (rc)
403 return rc;
404
405 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
406 ctrl_reg |= PM8xxx_RTC_ENABLE;
407 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
408 if (rc)
409 return rc;
410 }
411
412 return 0;
413 }
414
415 static const struct pm8xxx_rtc_regs pm8921_regs = {
416 .ctrl = 0x11d,
417 .write = 0x11f,
418 .read = 0x123,
419 .alarm_rw = 0x127,
420 .alarm_ctrl = 0x11d,
421 .alarm_ctrl2 = 0x11e,
422 .alarm_en = BIT(1),
423 };
424
425 static const struct pm8xxx_rtc_regs pm8058_regs = {
426 .ctrl = 0x1e8,
427 .write = 0x1ea,
428 .read = 0x1ee,
429 .alarm_rw = 0x1f2,
430 .alarm_ctrl = 0x1e8,
431 .alarm_ctrl2 = 0x1e9,
432 .alarm_en = BIT(1),
433 };
434
435 static const struct pm8xxx_rtc_regs pm8941_regs = {
436 .ctrl = 0x6046,
437 .write = 0x6040,
438 .read = 0x6048,
439 .alarm_rw = 0x6140,
440 .alarm_ctrl = 0x6146,
441 .alarm_ctrl2 = 0x6148,
442 .alarm_en = BIT(7),
443 };
444
445 /*
446 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
447 */
448 static const struct of_device_id pm8xxx_id_table[] = {
449 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
450 { .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs },
451 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
452 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
453 { },
454 };
455 MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
456
pm8xxx_rtc_probe(struct platform_device * pdev)457 static int pm8xxx_rtc_probe(struct platform_device *pdev)
458 {
459 int rc;
460 struct pm8xxx_rtc *rtc_dd;
461 const struct of_device_id *match;
462
463 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
464 if (!match)
465 return -ENXIO;
466
467 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
468 if (rtc_dd == NULL)
469 return -ENOMEM;
470
471 /* Initialise spinlock to protect RTC control register */
472 spin_lock_init(&rtc_dd->ctrl_reg_lock);
473
474 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
475 if (!rtc_dd->regmap) {
476 dev_err(&pdev->dev, "Parent regmap unavailable.\n");
477 return -ENXIO;
478 }
479
480 rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
481 if (rtc_dd->rtc_alarm_irq < 0) {
482 dev_err(&pdev->dev, "Alarm IRQ resource absent!\n");
483 return -ENXIO;
484 }
485
486 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
487 "allow-set-time");
488
489 rtc_dd->regs = match->data;
490 rtc_dd->rtc_dev = &pdev->dev;
491
492 rc = pm8xxx_rtc_enable(rtc_dd);
493 if (rc)
494 return rc;
495
496 platform_set_drvdata(pdev, rtc_dd);
497
498 device_init_wakeup(&pdev->dev, 1);
499
500 /* Register the RTC device */
501 rtc_dd->rtc = devm_rtc_device_register(&pdev->dev, "pm8xxx_rtc",
502 &pm8xxx_rtc_ops, THIS_MODULE);
503 if (IS_ERR(rtc_dd->rtc)) {
504 dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n",
505 __func__, PTR_ERR(rtc_dd->rtc));
506 return PTR_ERR(rtc_dd->rtc);
507 }
508
509 /* Request the alarm IRQ */
510 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
511 pm8xxx_alarm_trigger,
512 IRQF_TRIGGER_RISING,
513 "pm8xxx_rtc_alarm", rtc_dd);
514 if (rc < 0) {
515 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
516 return rc;
517 }
518
519 dev_dbg(&pdev->dev, "Probe success !!\n");
520
521 return 0;
522 }
523
524 #ifdef CONFIG_PM_SLEEP
pm8xxx_rtc_resume(struct device * dev)525 static int pm8xxx_rtc_resume(struct device *dev)
526 {
527 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
528
529 if (device_may_wakeup(dev))
530 disable_irq_wake(rtc_dd->rtc_alarm_irq);
531
532 return 0;
533 }
534
pm8xxx_rtc_suspend(struct device * dev)535 static int pm8xxx_rtc_suspend(struct device *dev)
536 {
537 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
538
539 if (device_may_wakeup(dev))
540 enable_irq_wake(rtc_dd->rtc_alarm_irq);
541
542 return 0;
543 }
544 #endif
545
546 static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
547 pm8xxx_rtc_suspend,
548 pm8xxx_rtc_resume);
549
550 static struct platform_driver pm8xxx_rtc_driver = {
551 .probe = pm8xxx_rtc_probe,
552 .driver = {
553 .name = "rtc-pm8xxx",
554 .pm = &pm8xxx_rtc_pm_ops,
555 .of_match_table = pm8xxx_id_table,
556 },
557 };
558
559 module_platform_driver(pm8xxx_rtc_driver);
560
561 MODULE_ALIAS("platform:rtc-pm8xxx");
562 MODULE_DESCRIPTION("PMIC8xxx RTC driver");
563 MODULE_LICENSE("GPL v2");
564 MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
565