1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
4 
5 #include <linux/init.h>
6 #include <linux/io.h>
7 #include <linux/kernel.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/rtc.h>
13 #include <linux/clk.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/regmap.h>
16 
17 #define SNVS_LPREGISTER_OFFSET	0x34
18 
19 /* These register offsets are relative to LP (Low Power) range */
20 #define SNVS_LPCR		0x04
21 #define SNVS_LPSR		0x18
22 #define SNVS_LPSRTCMR		0x1c
23 #define SNVS_LPSRTCLR		0x20
24 #define SNVS_LPTAR		0x24
25 #define SNVS_LPPGDR		0x30
26 
27 #define SNVS_LPCR_SRTC_ENV	(1 << 0)
28 #define SNVS_LPCR_LPTA_EN	(1 << 1)
29 #define SNVS_LPCR_LPWUI_EN	(1 << 3)
30 #define SNVS_LPSR_LPTA		(1 << 0)
31 
32 #define SNVS_LPPGDR_INIT	0x41736166
33 #define CNTR_TO_SECS_SH		15
34 
35 /* The maximum RTC clock cycles that are allowed to pass between two
36  * consecutive clock counter register reads. If the values are corrupted a
37  * bigger difference is expected. The RTC frequency is 32kHz. With 320 cycles
38  * we end at 10ms which should be enough for most cases. If it once takes
39  * longer than expected we do a retry.
40  */
41 #define MAX_RTC_READ_DIFF_CYCLES	320
42 
43 struct snvs_rtc_data {
44 	struct rtc_device *rtc;
45 	struct regmap *regmap;
46 	int offset;
47 	int irq;
48 	struct clk *clk;
49 };
50 
51 /* Read 64 bit timer register, which could be in inconsistent state */
rtc_read_lpsrt(struct snvs_rtc_data * data)52 static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
53 {
54 	u32 msb, lsb;
55 
56 	regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
57 	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
58 	return (u64)msb << 32 | lsb;
59 }
60 
61 /* Read the secure real time counter, taking care to deal with the cases of the
62  * counter updating while being read.
63  */
rtc_read_lp_counter(struct snvs_rtc_data * data)64 static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
65 {
66 	u64 read1, read2;
67 	s64 diff;
68 	unsigned int timeout = 100;
69 
70 	/* As expected, the registers might update between the read of the LSB
71 	 * reg and the MSB reg.  It's also possible that one register might be
72 	 * in partially modified state as well.
73 	 */
74 	read1 = rtc_read_lpsrt(data);
75 	do {
76 		read2 = read1;
77 		read1 = rtc_read_lpsrt(data);
78 		diff = read1 - read2;
79 	} while (((diff < 0) || (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout);
80 	if (!timeout)
81 		dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
82 
83 	/* Convert 47-bit counter to 32-bit raw second count */
84 	return (u32) (read1 >> CNTR_TO_SECS_SH);
85 }
86 
87 /* Just read the lsb from the counter, dealing with inconsistent state */
rtc_read_lp_counter_lsb(struct snvs_rtc_data * data,u32 * lsb)88 static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb)
89 {
90 	u32 count1, count2;
91 	s32 diff;
92 	unsigned int timeout = 100;
93 
94 	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
95 	do {
96 		count2 = count1;
97 		regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
98 		diff = count1 - count2;
99 	} while (((diff < 0) || (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout);
100 	if (!timeout) {
101 		dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
102 		return -ETIMEDOUT;
103 	}
104 
105 	*lsb = count1;
106 	return 0;
107 }
108 
rtc_write_sync_lp(struct snvs_rtc_data * data)109 static int rtc_write_sync_lp(struct snvs_rtc_data *data)
110 {
111 	u32 count1, count2;
112 	u32 elapsed;
113 	unsigned int timeout = 1000;
114 	int ret;
115 
116 	ret = rtc_read_lp_counter_lsb(data, &count1);
117 	if (ret)
118 		return ret;
119 
120 	/* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
121 	do {
122 		ret = rtc_read_lp_counter_lsb(data, &count2);
123 		if (ret)
124 			return ret;
125 		elapsed = count2 - count1; /* wrap around _is_ handled! */
126 	} while (elapsed < 3 && --timeout);
127 	if (!timeout) {
128 		dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
129 		return -ETIMEDOUT;
130 	}
131 	return 0;
132 }
133 
snvs_rtc_enable(struct snvs_rtc_data * data,bool enable)134 static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
135 {
136 	int timeout = 1000;
137 	u32 lpcr;
138 
139 	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
140 			   enable ? SNVS_LPCR_SRTC_ENV : 0);
141 
142 	while (--timeout) {
143 		regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
144 
145 		if (enable) {
146 			if (lpcr & SNVS_LPCR_SRTC_ENV)
147 				break;
148 		} else {
149 			if (!(lpcr & SNVS_LPCR_SRTC_ENV))
150 				break;
151 		}
152 	}
153 
154 	if (!timeout)
155 		return -ETIMEDOUT;
156 
157 	return 0;
158 }
159 
snvs_rtc_read_time(struct device * dev,struct rtc_time * tm)160 static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
161 {
162 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
163 	unsigned long time = rtc_read_lp_counter(data);
164 
165 	rtc_time_to_tm(time, tm);
166 
167 	return 0;
168 }
169 
snvs_rtc_set_time(struct device * dev,struct rtc_time * tm)170 static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
171 {
172 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
173 	unsigned long time;
174 	int ret;
175 
176 	rtc_tm_to_time(tm, &time);
177 
178 	/* Disable RTC first */
179 	ret = snvs_rtc_enable(data, false);
180 	if (ret)
181 		return ret;
182 
183 	/* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
184 	regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
185 	regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
186 
187 	/* Enable RTC again */
188 	ret = snvs_rtc_enable(data, true);
189 
190 	return ret;
191 }
192 
snvs_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)193 static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
194 {
195 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
196 	u32 lptar, lpsr;
197 
198 	regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
199 	rtc_time_to_tm(lptar, &alrm->time);
200 
201 	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
202 	alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
203 
204 	return 0;
205 }
206 
snvs_rtc_alarm_irq_enable(struct device * dev,unsigned int enable)207 static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
208 {
209 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
210 
211 	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
212 			   (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
213 			   enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);
214 
215 	return rtc_write_sync_lp(data);
216 }
217 
snvs_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)218 static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
219 {
220 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
221 	struct rtc_time *alrm_tm = &alrm->time;
222 	unsigned long time;
223 	int ret;
224 
225 	rtc_tm_to_time(alrm_tm, &time);
226 
227 	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
228 	ret = rtc_write_sync_lp(data);
229 	if (ret)
230 		return ret;
231 	regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
232 
233 	/* Clear alarm interrupt status bit */
234 	regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
235 
236 	return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
237 }
238 
239 static const struct rtc_class_ops snvs_rtc_ops = {
240 	.read_time = snvs_rtc_read_time,
241 	.set_time = snvs_rtc_set_time,
242 	.read_alarm = snvs_rtc_read_alarm,
243 	.set_alarm = snvs_rtc_set_alarm,
244 	.alarm_irq_enable = snvs_rtc_alarm_irq_enable,
245 };
246 
snvs_rtc_irq_handler(int irq,void * dev_id)247 static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
248 {
249 	struct device *dev = dev_id;
250 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
251 	u32 lpsr;
252 	u32 events = 0;
253 
254 	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
255 
256 	if (lpsr & SNVS_LPSR_LPTA) {
257 		events |= (RTC_AF | RTC_IRQF);
258 
259 		/* RTC alarm should be one-shot */
260 		snvs_rtc_alarm_irq_enable(dev, 0);
261 
262 		rtc_update_irq(data->rtc, 1, events);
263 	}
264 
265 	/* clear interrupt status */
266 	regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
267 
268 	return events ? IRQ_HANDLED : IRQ_NONE;
269 }
270 
271 static const struct regmap_config snvs_rtc_config = {
272 	.reg_bits = 32,
273 	.val_bits = 32,
274 	.reg_stride = 4,
275 };
276 
snvs_rtc_probe(struct platform_device * pdev)277 static int snvs_rtc_probe(struct platform_device *pdev)
278 {
279 	struct snvs_rtc_data *data;
280 	struct resource *res;
281 	int ret;
282 	void __iomem *mmio;
283 
284 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
285 	if (!data)
286 		return -ENOMEM;
287 
288 	data->rtc = devm_rtc_allocate_device(&pdev->dev);
289 	if (IS_ERR(data->rtc))
290 		return PTR_ERR(data->rtc);
291 
292 	data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
293 
294 	if (IS_ERR(data->regmap)) {
295 		dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
296 		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
297 
298 		mmio = devm_ioremap_resource(&pdev->dev, res);
299 		if (IS_ERR(mmio))
300 			return PTR_ERR(mmio);
301 
302 		data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
303 	} else {
304 		data->offset = SNVS_LPREGISTER_OFFSET;
305 		of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
306 	}
307 
308 	if (IS_ERR(data->regmap)) {
309 		dev_err(&pdev->dev, "Can't find snvs syscon\n");
310 		return -ENODEV;
311 	}
312 
313 	data->irq = platform_get_irq(pdev, 0);
314 	if (data->irq < 0)
315 		return data->irq;
316 
317 	data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
318 	if (IS_ERR(data->clk)) {
319 		data->clk = NULL;
320 	} else {
321 		ret = clk_prepare_enable(data->clk);
322 		if (ret) {
323 			dev_err(&pdev->dev,
324 				"Could not prepare or enable the snvs clock\n");
325 			return ret;
326 		}
327 	}
328 
329 	platform_set_drvdata(pdev, data);
330 
331 	/* Initialize glitch detect */
332 	regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
333 
334 	/* Clear interrupt status */
335 	regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
336 
337 	/* Enable RTC */
338 	ret = snvs_rtc_enable(data, true);
339 	if (ret) {
340 		dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
341 		goto error_rtc_device_register;
342 	}
343 
344 	device_init_wakeup(&pdev->dev, true);
345 
346 	ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
347 			       IRQF_SHARED, "rtc alarm", &pdev->dev);
348 	if (ret) {
349 		dev_err(&pdev->dev, "failed to request irq %d: %d\n",
350 			data->irq, ret);
351 		goto error_rtc_device_register;
352 	}
353 
354 	data->rtc->ops = &snvs_rtc_ops;
355 	ret = rtc_register_device(data->rtc);
356 	if (ret) {
357 		dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
358 		goto error_rtc_device_register;
359 	}
360 
361 	return 0;
362 
363 error_rtc_device_register:
364 	if (data->clk)
365 		clk_disable_unprepare(data->clk);
366 
367 	return ret;
368 }
369 
370 #ifdef CONFIG_PM_SLEEP
snvs_rtc_suspend(struct device * dev)371 static int snvs_rtc_suspend(struct device *dev)
372 {
373 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
374 
375 	if (device_may_wakeup(dev))
376 		return enable_irq_wake(data->irq);
377 
378 	return 0;
379 }
380 
snvs_rtc_suspend_noirq(struct device * dev)381 static int snvs_rtc_suspend_noirq(struct device *dev)
382 {
383 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
384 
385 	if (data->clk)
386 		clk_disable_unprepare(data->clk);
387 
388 	return 0;
389 }
390 
snvs_rtc_resume(struct device * dev)391 static int snvs_rtc_resume(struct device *dev)
392 {
393 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
394 
395 	if (device_may_wakeup(dev))
396 		return disable_irq_wake(data->irq);
397 
398 	return 0;
399 }
400 
snvs_rtc_resume_noirq(struct device * dev)401 static int snvs_rtc_resume_noirq(struct device *dev)
402 {
403 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
404 
405 	if (data->clk)
406 		return clk_prepare_enable(data->clk);
407 
408 	return 0;
409 }
410 
411 static const struct dev_pm_ops snvs_rtc_pm_ops = {
412 	.suspend = snvs_rtc_suspend,
413 	.suspend_noirq = snvs_rtc_suspend_noirq,
414 	.resume = snvs_rtc_resume,
415 	.resume_noirq = snvs_rtc_resume_noirq,
416 };
417 
418 #define SNVS_RTC_PM_OPS	(&snvs_rtc_pm_ops)
419 
420 #else
421 
422 #define SNVS_RTC_PM_OPS	NULL
423 
424 #endif
425 
426 static const struct of_device_id snvs_dt_ids[] = {
427 	{ .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
428 	{ /* sentinel */ }
429 };
430 MODULE_DEVICE_TABLE(of, snvs_dt_ids);
431 
432 static struct platform_driver snvs_rtc_driver = {
433 	.driver = {
434 		.name	= "snvs_rtc",
435 		.pm	= SNVS_RTC_PM_OPS,
436 		.of_match_table = snvs_dt_ids,
437 	},
438 	.probe		= snvs_rtc_probe,
439 };
440 module_platform_driver(snvs_rtc_driver);
441 
442 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
443 MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
444 MODULE_LICENSE("GPL");
445