1 /*
2  * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
3  *
4  * Copyright (c) 2010, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20 
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mod_devicetable.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm.h>
31 #include <linux/rtc.h>
32 #include <linux/slab.h>
33 
34 /* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */
35 #define TEGRA_RTC_REG_BUSY			0x004
36 #define TEGRA_RTC_REG_SECONDS			0x008
37 /* when msec is read, the seconds are buffered into shadow seconds. */
38 #define TEGRA_RTC_REG_SHADOW_SECONDS		0x00c
39 #define TEGRA_RTC_REG_MILLI_SECONDS		0x010
40 #define TEGRA_RTC_REG_SECONDS_ALARM0		0x014
41 #define TEGRA_RTC_REG_SECONDS_ALARM1		0x018
42 #define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0	0x01c
43 #define TEGRA_RTC_REG_INTR_MASK			0x028
44 /* write 1 bits to clear status bits */
45 #define TEGRA_RTC_REG_INTR_STATUS		0x02c
46 
47 /* bits in INTR_MASK */
48 #define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM	(1<<4)
49 #define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM	(1<<3)
50 #define TEGRA_RTC_INTR_MASK_MSEC_ALARM		(1<<2)
51 #define TEGRA_RTC_INTR_MASK_SEC_ALARM1		(1<<1)
52 #define TEGRA_RTC_INTR_MASK_SEC_ALARM0		(1<<0)
53 
54 /* bits in INTR_STATUS */
55 #define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM	(1<<4)
56 #define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM	(1<<3)
57 #define TEGRA_RTC_INTR_STATUS_MSEC_ALARM	(1<<2)
58 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM1	(1<<1)
59 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM0	(1<<0)
60 
61 struct tegra_rtc_info {
62 	struct platform_device	*pdev;
63 	struct rtc_device	*rtc_dev;
64 	void __iomem		*rtc_base; /* NULL if not initialized. */
65 	struct clk		*clk;
66 	int			tegra_rtc_irq; /* alarm and periodic irq */
67 	spinlock_t		tegra_rtc_lock;
68 };
69 
70 /* RTC hardware is busy when it is updating its values over AHB once
71  * every eight 32kHz clocks (~250uS).
72  * outside of these updates the CPU is free to write.
73  * CPU is always free to read.
74  */
tegra_rtc_check_busy(struct tegra_rtc_info * info)75 static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
76 {
77 	return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1;
78 }
79 
80 /* Wait for hardware to be ready for writing.
81  * This function tries to maximize the amount of time before the next update.
82  * It does this by waiting for the RTC to become busy with its periodic update,
83  * then returning once the RTC first becomes not busy.
84  * This periodic update (where the seconds and milliseconds are copied to the
85  * AHB side) occurs every eight 32kHz clocks (~250uS).
86  * The behavior of this function allows us to make some assumptions without
87  * introducing a race, because 250uS is plenty of time to read/write a value.
88  */
tegra_rtc_wait_while_busy(struct device * dev)89 static int tegra_rtc_wait_while_busy(struct device *dev)
90 {
91 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
92 
93 	int retries = 500; /* ~490 us is the worst case, ~250 us is best. */
94 
95 	/* first wait for the RTC to become busy. this is when it
96 	 * posts its updated seconds+msec registers to AHB side. */
97 	while (tegra_rtc_check_busy(info)) {
98 		if (!retries--)
99 			goto retry_failed;
100 		udelay(1);
101 	}
102 
103 	/* now we have about 250 us to manipulate registers */
104 	return 0;
105 
106 retry_failed:
107 	dev_err(dev, "write failed:retry count exceeded.\n");
108 	return -ETIMEDOUT;
109 }
110 
tegra_rtc_read_time(struct device * dev,struct rtc_time * tm)111 static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
112 {
113 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
114 	unsigned long sec, msec;
115 	unsigned long sl_irq_flags;
116 
117 	/* RTC hardware copies seconds to shadow seconds when a read
118 	 * of milliseconds occurs. use a lock to keep other threads out. */
119 	spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
120 
121 	msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS);
122 	sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS);
123 
124 	spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
125 
126 	rtc_time_to_tm(sec, tm);
127 
128 	dev_vdbg(dev, "time read as %lu. %d/%d/%d %d:%02u:%02u\n",
129 		sec,
130 		tm->tm_mon + 1,
131 		tm->tm_mday,
132 		tm->tm_year + 1900,
133 		tm->tm_hour,
134 		tm->tm_min,
135 		tm->tm_sec
136 	);
137 
138 	return 0;
139 }
140 
tegra_rtc_set_time(struct device * dev,struct rtc_time * tm)141 static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
142 {
143 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
144 	unsigned long sec;
145 	int ret;
146 
147 	/* convert tm to seconds. */
148 	rtc_tm_to_time(tm, &sec);
149 
150 	dev_vdbg(dev, "time set to %lu. %d/%d/%d %d:%02u:%02u\n",
151 		sec,
152 		tm->tm_mon+1,
153 		tm->tm_mday,
154 		tm->tm_year+1900,
155 		tm->tm_hour,
156 		tm->tm_min,
157 		tm->tm_sec
158 	);
159 
160 	/* seconds only written if wait succeeded. */
161 	ret = tegra_rtc_wait_while_busy(dev);
162 	if (!ret)
163 		writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS);
164 
165 	dev_vdbg(dev, "time read back as %d\n",
166 		readl(info->rtc_base + TEGRA_RTC_REG_SECONDS));
167 
168 	return ret;
169 }
170 
tegra_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alarm)171 static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
172 {
173 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
174 	unsigned long sec;
175 	unsigned tmp;
176 
177 	sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
178 
179 	if (sec == 0) {
180 		/* alarm is disabled. */
181 		alarm->enabled = 0;
182 	} else {
183 		/* alarm is enabled. */
184 		alarm->enabled = 1;
185 		rtc_time_to_tm(sec, &alarm->time);
186 	}
187 
188 	tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
189 	alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
190 
191 	return 0;
192 }
193 
tegra_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)194 static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
195 {
196 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
197 	unsigned status;
198 	unsigned long sl_irq_flags;
199 
200 	tegra_rtc_wait_while_busy(dev);
201 	spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
202 
203 	/* read the original value, and OR in the flag. */
204 	status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
205 	if (enabled)
206 		status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
207 	else
208 		status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
209 
210 	writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
211 
212 	spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
213 
214 	return 0;
215 }
216 
tegra_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alarm)217 static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
218 {
219 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
220 	unsigned long sec;
221 
222 	if (alarm->enabled)
223 		rtc_tm_to_time(&alarm->time, &sec);
224 	else
225 		sec = 0;
226 
227 	tegra_rtc_wait_while_busy(dev);
228 	writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
229 	dev_vdbg(dev, "alarm read back as %d\n",
230 		readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
231 
232 	/* if successfully written and alarm is enabled ... */
233 	if (sec) {
234 		tegra_rtc_alarm_irq_enable(dev, 1);
235 
236 		dev_vdbg(dev, "alarm set as %lu. %d/%d/%d %d:%02u:%02u\n",
237 			sec,
238 			alarm->time.tm_mon+1,
239 			alarm->time.tm_mday,
240 			alarm->time.tm_year+1900,
241 			alarm->time.tm_hour,
242 			alarm->time.tm_min,
243 			alarm->time.tm_sec);
244 	} else {
245 		/* disable alarm if 0 or write error. */
246 		dev_vdbg(dev, "alarm disabled\n");
247 		tegra_rtc_alarm_irq_enable(dev, 0);
248 	}
249 
250 	return 0;
251 }
252 
tegra_rtc_proc(struct device * dev,struct seq_file * seq)253 static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
254 {
255 	if (!dev || !dev->driver)
256 		return 0;
257 
258 	seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
259 
260 	return 0;
261 }
262 
tegra_rtc_irq_handler(int irq,void * data)263 static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
264 {
265 	struct device *dev = data;
266 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
267 	unsigned long events = 0;
268 	unsigned status;
269 	unsigned long sl_irq_flags;
270 
271 	status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
272 	if (status) {
273 		/* clear the interrupt masks and status on any irq. */
274 		tegra_rtc_wait_while_busy(dev);
275 		spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
276 		writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
277 		writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
278 		spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
279 	}
280 
281 	/* check if Alarm */
282 	if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0))
283 		events |= RTC_IRQF | RTC_AF;
284 
285 	/* check if Periodic */
286 	if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM))
287 		events |= RTC_IRQF | RTC_PF;
288 
289 	rtc_update_irq(info->rtc_dev, 1, events);
290 
291 	return IRQ_HANDLED;
292 }
293 
294 static const struct rtc_class_ops tegra_rtc_ops = {
295 	.read_time	= tegra_rtc_read_time,
296 	.set_time	= tegra_rtc_set_time,
297 	.read_alarm	= tegra_rtc_read_alarm,
298 	.set_alarm	= tegra_rtc_set_alarm,
299 	.proc		= tegra_rtc_proc,
300 	.alarm_irq_enable = tegra_rtc_alarm_irq_enable,
301 };
302 
303 static const struct of_device_id tegra_rtc_dt_match[] = {
304 	{ .compatible = "nvidia,tegra20-rtc", },
305 	{}
306 };
307 MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
308 
tegra_rtc_probe(struct platform_device * pdev)309 static int __init tegra_rtc_probe(struct platform_device *pdev)
310 {
311 	struct tegra_rtc_info *info;
312 	struct resource *res;
313 	int ret;
314 
315 	info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info),
316 		GFP_KERNEL);
317 	if (!info)
318 		return -ENOMEM;
319 
320 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
321 	info->rtc_base = devm_ioremap_resource(&pdev->dev, res);
322 	if (IS_ERR(info->rtc_base))
323 		return PTR_ERR(info->rtc_base);
324 
325 	info->tegra_rtc_irq = platform_get_irq(pdev, 0);
326 	if (info->tegra_rtc_irq <= 0)
327 		return -EBUSY;
328 
329 	info->clk = devm_clk_get(&pdev->dev, NULL);
330 	if (IS_ERR(info->clk))
331 		return PTR_ERR(info->clk);
332 
333 	ret = clk_prepare_enable(info->clk);
334 	if (ret < 0)
335 		return ret;
336 
337 	/* set context info. */
338 	info->pdev = pdev;
339 	spin_lock_init(&info->tegra_rtc_lock);
340 
341 	platform_set_drvdata(pdev, info);
342 
343 	/* clear out the hardware. */
344 	writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
345 	writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
346 	writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
347 
348 	device_init_wakeup(&pdev->dev, 1);
349 
350 	info->rtc_dev = devm_rtc_device_register(&pdev->dev,
351 				dev_name(&pdev->dev), &tegra_rtc_ops,
352 				THIS_MODULE);
353 	if (IS_ERR(info->rtc_dev)) {
354 		ret = PTR_ERR(info->rtc_dev);
355 		dev_err(&pdev->dev, "Unable to register device (err=%d).\n",
356 			ret);
357 		goto disable_clk;
358 	}
359 
360 	ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq,
361 			tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH,
362 			dev_name(&pdev->dev), &pdev->dev);
363 	if (ret) {
364 		dev_err(&pdev->dev,
365 			"Unable to request interrupt for device (err=%d).\n",
366 			ret);
367 		goto disable_clk;
368 	}
369 
370 	dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
371 
372 	return 0;
373 
374 disable_clk:
375 	clk_disable_unprepare(info->clk);
376 	return ret;
377 }
378 
tegra_rtc_remove(struct platform_device * pdev)379 static int tegra_rtc_remove(struct platform_device *pdev)
380 {
381 	struct tegra_rtc_info *info = platform_get_drvdata(pdev);
382 
383 	clk_disable_unprepare(info->clk);
384 
385 	return 0;
386 }
387 
388 #ifdef CONFIG_PM_SLEEP
tegra_rtc_suspend(struct device * dev)389 static int tegra_rtc_suspend(struct device *dev)
390 {
391 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
392 
393 	tegra_rtc_wait_while_busy(dev);
394 
395 	/* only use ALARM0 as a wake source. */
396 	writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
397 	writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
398 		info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
399 
400 	dev_vdbg(dev, "alarm sec = %d\n",
401 		readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
402 
403 	dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n",
404 		device_may_wakeup(dev), info->tegra_rtc_irq);
405 
406 	/* leave the alarms on as a wake source. */
407 	if (device_may_wakeup(dev))
408 		enable_irq_wake(info->tegra_rtc_irq);
409 
410 	return 0;
411 }
412 
tegra_rtc_resume(struct device * dev)413 static int tegra_rtc_resume(struct device *dev)
414 {
415 	struct tegra_rtc_info *info = dev_get_drvdata(dev);
416 
417 	dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
418 		device_may_wakeup(dev));
419 	/* alarms were left on as a wake source, turn them off. */
420 	if (device_may_wakeup(dev))
421 		disable_irq_wake(info->tegra_rtc_irq);
422 
423 	return 0;
424 }
425 #endif
426 
427 static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
428 
tegra_rtc_shutdown(struct platform_device * pdev)429 static void tegra_rtc_shutdown(struct platform_device *pdev)
430 {
431 	dev_vdbg(&pdev->dev, "disabling interrupts.\n");
432 	tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
433 }
434 
435 MODULE_ALIAS("platform:tegra_rtc");
436 static struct platform_driver tegra_rtc_driver = {
437 	.remove		= tegra_rtc_remove,
438 	.shutdown	= tegra_rtc_shutdown,
439 	.driver		= {
440 		.name	= "tegra_rtc",
441 		.of_match_table = tegra_rtc_dt_match,
442 		.pm	= &tegra_rtc_pm_ops,
443 	},
444 };
445 
446 module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe);
447 
448 MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
449 MODULE_DESCRIPTION("driver for Tegra internal RTC");
450 MODULE_LICENSE("GPL");
451