1 /*
2  * Copyright 2017 Texas Instruments, Inc.
3  *
4  * This software is licensed under the terms of the GNU General Public
5  * License version 2, as published by the Free Software Foundation, and
6  * may be copied, distributed, and modified under those terms.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
13 #ifndef __DT_BINDINGS_CLK_AM4_H
14 #define __DT_BINDINGS_CLK_AM4_H
15 
16 #define AM4_CLKCTRL_OFFSET	0x20
17 #define AM4_CLKCTRL_INDEX(offset)	((offset) - AM4_CLKCTRL_OFFSET)
18 
19 /* l4_wkup clocks */
20 #define AM4_ADC_TSC_CLKCTRL	AM4_CLKCTRL_INDEX(0x120)
21 #define AM4_L4_WKUP_CLKCTRL	AM4_CLKCTRL_INDEX(0x220)
22 #define AM4_WKUP_M3_CLKCTRL	AM4_CLKCTRL_INDEX(0x228)
23 #define AM4_COUNTER_32K_CLKCTRL	AM4_CLKCTRL_INDEX(0x230)
24 #define AM4_TIMER1_CLKCTRL	AM4_CLKCTRL_INDEX(0x328)
25 #define AM4_WD_TIMER2_CLKCTRL	AM4_CLKCTRL_INDEX(0x338)
26 #define AM4_I2C1_CLKCTRL	AM4_CLKCTRL_INDEX(0x340)
27 #define AM4_UART1_CLKCTRL	AM4_CLKCTRL_INDEX(0x348)
28 #define AM4_SMARTREFLEX0_CLKCTRL	AM4_CLKCTRL_INDEX(0x350)
29 #define AM4_SMARTREFLEX1_CLKCTRL	AM4_CLKCTRL_INDEX(0x358)
30 #define AM4_CONTROL_CLKCTRL	AM4_CLKCTRL_INDEX(0x360)
31 #define AM4_GPIO1_CLKCTRL	AM4_CLKCTRL_INDEX(0x368)
32 
33 /* mpu clocks */
34 #define AM4_MPU_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
35 
36 /* gfx_l3 clocks */
37 #define AM4_GFX_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
38 
39 /* l4_rtc clocks */
40 #define AM4_RTC_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
41 
42 /* l4_per clocks */
43 #define AM4_L3_MAIN_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
44 #define AM4_AES_CLKCTRL	AM4_CLKCTRL_INDEX(0x28)
45 #define AM4_DES_CLKCTRL	AM4_CLKCTRL_INDEX(0x30)
46 #define AM4_L3_INSTR_CLKCTRL	AM4_CLKCTRL_INDEX(0x40)
47 #define AM4_OCMCRAM_CLKCTRL	AM4_CLKCTRL_INDEX(0x50)
48 #define AM4_SHAM_CLKCTRL	AM4_CLKCTRL_INDEX(0x58)
49 #define AM4_VPFE0_CLKCTRL	AM4_CLKCTRL_INDEX(0x68)
50 #define AM4_VPFE1_CLKCTRL	AM4_CLKCTRL_INDEX(0x70)
51 #define AM4_TPCC_CLKCTRL	AM4_CLKCTRL_INDEX(0x78)
52 #define AM4_TPTC0_CLKCTRL	AM4_CLKCTRL_INDEX(0x80)
53 #define AM4_TPTC1_CLKCTRL	AM4_CLKCTRL_INDEX(0x88)
54 #define AM4_TPTC2_CLKCTRL	AM4_CLKCTRL_INDEX(0x90)
55 #define AM4_L4_HS_CLKCTRL	AM4_CLKCTRL_INDEX(0xa0)
56 #define AM4_GPMC_CLKCTRL	AM4_CLKCTRL_INDEX(0x220)
57 #define AM4_MCASP0_CLKCTRL	AM4_CLKCTRL_INDEX(0x238)
58 #define AM4_MCASP1_CLKCTRL	AM4_CLKCTRL_INDEX(0x240)
59 #define AM4_MMC3_CLKCTRL	AM4_CLKCTRL_INDEX(0x248)
60 #define AM4_QSPI_CLKCTRL	AM4_CLKCTRL_INDEX(0x258)
61 #define AM4_USB_OTG_SS0_CLKCTRL	AM4_CLKCTRL_INDEX(0x260)
62 #define AM4_USB_OTG_SS1_CLKCTRL	AM4_CLKCTRL_INDEX(0x268)
63 #define AM4_PRUSS_CLKCTRL	AM4_CLKCTRL_INDEX(0x320)
64 #define AM4_L4_LS_CLKCTRL	AM4_CLKCTRL_INDEX(0x420)
65 #define AM4_D_CAN0_CLKCTRL	AM4_CLKCTRL_INDEX(0x428)
66 #define AM4_D_CAN1_CLKCTRL	AM4_CLKCTRL_INDEX(0x430)
67 #define AM4_EPWMSS0_CLKCTRL	AM4_CLKCTRL_INDEX(0x438)
68 #define AM4_EPWMSS1_CLKCTRL	AM4_CLKCTRL_INDEX(0x440)
69 #define AM4_EPWMSS2_CLKCTRL	AM4_CLKCTRL_INDEX(0x448)
70 #define AM4_EPWMSS3_CLKCTRL	AM4_CLKCTRL_INDEX(0x450)
71 #define AM4_EPWMSS4_CLKCTRL	AM4_CLKCTRL_INDEX(0x458)
72 #define AM4_EPWMSS5_CLKCTRL	AM4_CLKCTRL_INDEX(0x460)
73 #define AM4_ELM_CLKCTRL	AM4_CLKCTRL_INDEX(0x468)
74 #define AM4_GPIO2_CLKCTRL	AM4_CLKCTRL_INDEX(0x478)
75 #define AM4_GPIO3_CLKCTRL	AM4_CLKCTRL_INDEX(0x480)
76 #define AM4_GPIO4_CLKCTRL	AM4_CLKCTRL_INDEX(0x488)
77 #define AM4_GPIO5_CLKCTRL	AM4_CLKCTRL_INDEX(0x490)
78 #define AM4_GPIO6_CLKCTRL	AM4_CLKCTRL_INDEX(0x498)
79 #define AM4_HDQ1W_CLKCTRL	AM4_CLKCTRL_INDEX(0x4a0)
80 #define AM4_I2C2_CLKCTRL	AM4_CLKCTRL_INDEX(0x4a8)
81 #define AM4_I2C3_CLKCTRL	AM4_CLKCTRL_INDEX(0x4b0)
82 #define AM4_MAILBOX_CLKCTRL	AM4_CLKCTRL_INDEX(0x4b8)
83 #define AM4_MMC1_CLKCTRL	AM4_CLKCTRL_INDEX(0x4c0)
84 #define AM4_MMC2_CLKCTRL	AM4_CLKCTRL_INDEX(0x4c8)
85 #define AM4_RNG_CLKCTRL	AM4_CLKCTRL_INDEX(0x4e0)
86 #define AM4_SPI0_CLKCTRL	AM4_CLKCTRL_INDEX(0x500)
87 #define AM4_SPI1_CLKCTRL	AM4_CLKCTRL_INDEX(0x508)
88 #define AM4_SPI2_CLKCTRL	AM4_CLKCTRL_INDEX(0x510)
89 #define AM4_SPI3_CLKCTRL	AM4_CLKCTRL_INDEX(0x518)
90 #define AM4_SPI4_CLKCTRL	AM4_CLKCTRL_INDEX(0x520)
91 #define AM4_SPINLOCK_CLKCTRL	AM4_CLKCTRL_INDEX(0x528)
92 #define AM4_TIMER2_CLKCTRL	AM4_CLKCTRL_INDEX(0x530)
93 #define AM4_TIMER3_CLKCTRL	AM4_CLKCTRL_INDEX(0x538)
94 #define AM4_TIMER4_CLKCTRL	AM4_CLKCTRL_INDEX(0x540)
95 #define AM4_TIMER5_CLKCTRL	AM4_CLKCTRL_INDEX(0x548)
96 #define AM4_TIMER6_CLKCTRL	AM4_CLKCTRL_INDEX(0x550)
97 #define AM4_TIMER7_CLKCTRL	AM4_CLKCTRL_INDEX(0x558)
98 #define AM4_TIMER8_CLKCTRL	AM4_CLKCTRL_INDEX(0x560)
99 #define AM4_TIMER9_CLKCTRL	AM4_CLKCTRL_INDEX(0x568)
100 #define AM4_TIMER10_CLKCTRL	AM4_CLKCTRL_INDEX(0x570)
101 #define AM4_TIMER11_CLKCTRL	AM4_CLKCTRL_INDEX(0x578)
102 #define AM4_UART2_CLKCTRL	AM4_CLKCTRL_INDEX(0x580)
103 #define AM4_UART3_CLKCTRL	AM4_CLKCTRL_INDEX(0x588)
104 #define AM4_UART4_CLKCTRL	AM4_CLKCTRL_INDEX(0x590)
105 #define AM4_UART5_CLKCTRL	AM4_CLKCTRL_INDEX(0x598)
106 #define AM4_UART6_CLKCTRL	AM4_CLKCTRL_INDEX(0x5a0)
107 #define AM4_OCP2SCP0_CLKCTRL	AM4_CLKCTRL_INDEX(0x5b8)
108 #define AM4_OCP2SCP1_CLKCTRL	AM4_CLKCTRL_INDEX(0x5c0)
109 #define AM4_EMIF_CLKCTRL	AM4_CLKCTRL_INDEX(0x720)
110 #define AM4_DSS_CORE_CLKCTRL	AM4_CLKCTRL_INDEX(0xa20)
111 #define AM4_CPGMAC0_CLKCTRL	AM4_CLKCTRL_INDEX(0xb20)
112 
113 #endif
114