1 /* 2 * Copyright (c) 2012-2013 Hisilicon Limited. 3 * Copyright (c) 2012-2013 Linaro Limited. 4 * 5 * Author: Haojian Zhuang <haojian.zhuang@linaro.org> 6 * Xin Li <li.xin@linaro.org> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, write to the Free Software Foundation, Inc., 20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21 * 22 */ 23 24 #ifndef __DTS_HI3620_CLOCK_H 25 #define __DTS_HI3620_CLOCK_H 26 27 #define HI3620_NONE_CLOCK 0 28 29 /* fixed rate & fixed factor clocks */ 30 #define HI3620_OSC32K 1 31 #define HI3620_OSC26M 2 32 #define HI3620_PCLK 3 33 #define HI3620_PLL_ARM0 4 34 #define HI3620_PLL_ARM1 5 35 #define HI3620_PLL_PERI 6 36 #define HI3620_PLL_USB 7 37 #define HI3620_PLL_HDMI 8 38 #define HI3620_PLL_GPU 9 39 #define HI3620_RCLK_TCXO 10 40 #define HI3620_RCLK_CFGAXI 11 41 #define HI3620_RCLK_PICO 12 42 43 /* mux clocks */ 44 #define HI3620_TIMER0_MUX 32 45 #define HI3620_TIMER1_MUX 33 46 #define HI3620_TIMER2_MUX 34 47 #define HI3620_TIMER3_MUX 35 48 #define HI3620_TIMER4_MUX 36 49 #define HI3620_TIMER5_MUX 37 50 #define HI3620_TIMER6_MUX 38 51 #define HI3620_TIMER7_MUX 39 52 #define HI3620_TIMER8_MUX 40 53 #define HI3620_TIMER9_MUX 41 54 #define HI3620_UART0_MUX 42 55 #define HI3620_UART1_MUX 43 56 #define HI3620_UART2_MUX 44 57 #define HI3620_UART3_MUX 45 58 #define HI3620_UART4_MUX 46 59 #define HI3620_SPI0_MUX 47 60 #define HI3620_SPI1_MUX 48 61 #define HI3620_SPI2_MUX 49 62 #define HI3620_SAXI_MUX 50 63 #define HI3620_PWM0_MUX 51 64 #define HI3620_PWM1_MUX 52 65 #define HI3620_SD_MUX 53 66 #define HI3620_MMC1_MUX 54 67 #define HI3620_MMC1_MUX2 55 68 #define HI3620_G2D_MUX 56 69 #define HI3620_VENC_MUX 57 70 #define HI3620_VDEC_MUX 58 71 #define HI3620_VPP_MUX 59 72 #define HI3620_EDC0_MUX 60 73 #define HI3620_LDI0_MUX 61 74 #define HI3620_EDC1_MUX 62 75 #define HI3620_LDI1_MUX 63 76 #define HI3620_RCLK_HSIC 64 77 #define HI3620_MMC2_MUX 65 78 #define HI3620_MMC3_MUX 66 79 80 /* divider clocks */ 81 #define HI3620_SHAREAXI_DIV 128 82 #define HI3620_CFGAXI_DIV 129 83 #define HI3620_SD_DIV 130 84 #define HI3620_MMC1_DIV 131 85 #define HI3620_HSIC_DIV 132 86 #define HI3620_MMC2_DIV 133 87 #define HI3620_MMC3_DIV 134 88 89 /* gate clocks */ 90 #define HI3620_TIMERCLK01 160 91 #define HI3620_TIMER_RCLK01 161 92 #define HI3620_TIMERCLK23 162 93 #define HI3620_TIMER_RCLK23 163 94 #define HI3620_TIMERCLK45 164 95 #define HI3620_TIMERCLK67 165 96 #define HI3620_TIMERCLK89 166 97 #define HI3620_RTCCLK 167 98 #define HI3620_KPC_CLK 168 99 #define HI3620_GPIOCLK0 169 100 #define HI3620_GPIOCLK1 170 101 #define HI3620_GPIOCLK2 171 102 #define HI3620_GPIOCLK3 172 103 #define HI3620_GPIOCLK4 173 104 #define HI3620_GPIOCLK5 174 105 #define HI3620_GPIOCLK6 175 106 #define HI3620_GPIOCLK7 176 107 #define HI3620_GPIOCLK8 177 108 #define HI3620_GPIOCLK9 178 109 #define HI3620_GPIOCLK10 179 110 #define HI3620_GPIOCLK11 180 111 #define HI3620_GPIOCLK12 181 112 #define HI3620_GPIOCLK13 182 113 #define HI3620_GPIOCLK14 183 114 #define HI3620_GPIOCLK15 184 115 #define HI3620_GPIOCLK16 185 116 #define HI3620_GPIOCLK17 186 117 #define HI3620_GPIOCLK18 187 118 #define HI3620_GPIOCLK19 188 119 #define HI3620_GPIOCLK20 189 120 #define HI3620_GPIOCLK21 190 121 #define HI3620_DPHY0_CLK 191 122 #define HI3620_DPHY1_CLK 192 123 #define HI3620_DPHY2_CLK 193 124 #define HI3620_USBPHY_CLK 194 125 #define HI3620_ACP_CLK 195 126 #define HI3620_PWMCLK0 196 127 #define HI3620_PWMCLK1 197 128 #define HI3620_UARTCLK0 198 129 #define HI3620_UARTCLK1 199 130 #define HI3620_UARTCLK2 200 131 #define HI3620_UARTCLK3 201 132 #define HI3620_UARTCLK4 202 133 #define HI3620_SPICLK0 203 134 #define HI3620_SPICLK1 204 135 #define HI3620_SPICLK2 205 136 #define HI3620_I2CCLK0 206 137 #define HI3620_I2CCLK1 207 138 #define HI3620_I2CCLK2 208 139 #define HI3620_I2CCLK3 209 140 #define HI3620_SCI_CLK 210 141 #define HI3620_DDRC_PER_CLK 211 142 #define HI3620_DMAC_CLK 212 143 #define HI3620_USB2DVC_CLK 213 144 #define HI3620_SD_CLK 214 145 #define HI3620_MMC_CLK1 215 146 #define HI3620_MMC_CLK2 216 147 #define HI3620_MMC_CLK3 217 148 #define HI3620_MCU_CLK 218 149 150 #define HI3620_SD_CIUCLK 0 151 #define HI3620_MMC_CIUCLK1 1 152 #define HI3620_MMC_CIUCLK2 2 153 #define HI3620_MMC_CIUCLK3 3 154 155 #define HI3620_NR_CLKS 219 156 157 #endif /* __DTS_HI3620_CLOCK_H */ 158