1 /* 2 * Copyright (C) 2015 - 2016 ZTE Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 #ifndef __DT_BINDINGS_CLOCK_ZX296718_H 9 #define __DT_BINDINGS_CLOCK_ZX296718_H 10 11 /* PLL */ 12 #define ZX296718_PLL_CPU 1 13 #define ZX296718_PLL_MAC 2 14 #define ZX296718_PLL_MM0 3 15 #define ZX296718_PLL_MM1 4 16 #define ZX296718_PLL_VGA 5 17 #define ZX296718_PLL_DDR 6 18 #define ZX296718_PLL_AUDIO 7 19 #define ZX296718_PLL_HSIC 8 20 #define CPU_DBG_GATE 9 21 #define A72_GATE 10 22 #define CPU_PERI_GATE 11 23 #define A53_GATE 12 24 #define DDR1_GATE 13 25 #define DDR0_GATE 14 26 #define SD1_WCLK 15 27 #define SD1_AHB 16 28 #define SD0_WCLK 17 29 #define SD0_AHB 18 30 #define EMMC_WCLK 19 31 #define EMMC_NAND_AXI 20 32 #define NAND_WCLK 21 33 #define EMMC_NAND_AHB 22 34 #define LSP1_148M5 23 35 #define LSP1_99M 24 36 #define LSP1_24M 25 37 #define LSP0_74M25 26 38 #define LSP0_32K 27 39 #define LSP0_148M5 28 40 #define LSP0_99M 29 41 #define LSP0_24M 30 42 #define DEMUX_AXI 31 43 #define DEMUX_APB 32 44 #define DEMUX_148M5 33 45 #define DEMUX_108M 34 46 #define AUDIO_APB 35 47 #define AUDIO_99M 36 48 #define AUDIO_24M 37 49 #define AUDIO_16M384 38 50 #define AUDIO_32K 39 51 #define WDT_WCLK 40 52 #define TIMER_WCLK 41 53 #define VDE_ACLK 42 54 #define VCE_ACLK 43 55 #define HDE_ACLK 44 56 #define GPU_ACLK 45 57 #define SAPPU_ACLK 46 58 #define SAPPU_WCLK 47 59 #define VOU_ACLK 48 60 #define VOU_MAIN_WCLK 49 61 #define VOU_AUX_WCLK 50 62 #define VOU_PPU_WCLK 51 63 #define MIPI_CFG_CLK 52 64 #define VGA_I2C_WCLK 53 65 #define MIPI_REF_CLK 54 66 #define HDMI_OSC_CEC 55 67 #define HDMI_OSC_CLK 56 68 #define HDMI_XCLK 57 69 #define VIU_M0_ACLK 58 70 #define VIU_M1_ACLK 59 71 #define VIU_WCLK 60 72 #define VIU_JPEG_WCLK 61 73 #define VIU_CFG_CLK 62 74 #define TS_SYS_WCLK 63 75 #define TS_SYS_108M 64 76 #define USB20_HCLK 65 77 #define USB20_PHY_CLK 66 78 #define USB21_HCLK 67 79 #define USB21_PHY_CLK 68 80 #define GMAC_RMIICLK 69 81 #define GMAC_PCLK 70 82 #define GMAC_ACLK 71 83 #define GMAC_RFCLK 72 84 #define TEMPSENSOR_GATE 73 85 86 #define TOP_NR_CLKS 74 87 88 89 #define LSP0_TIMER3_PCLK 1 90 #define LSP0_TIMER3_WCLK 2 91 #define LSP0_TIMER4_PCLK 3 92 #define LSP0_TIMER4_WCLK 4 93 #define LSP0_TIMER5_PCLK 5 94 #define LSP0_TIMER5_WCLK 6 95 #define LSP0_UART3_PCLK 7 96 #define LSP0_UART3_WCLK 8 97 #define LSP0_UART1_PCLK 9 98 #define LSP0_UART1_WCLK 10 99 #define LSP0_UART2_PCLK 11 100 #define LSP0_UART2_WCLK 12 101 #define LSP0_SPIFC0_PCLK 13 102 #define LSP0_SPIFC0_WCLK 14 103 #define LSP0_I2C4_PCLK 15 104 #define LSP0_I2C4_WCLK 16 105 #define LSP0_I2C5_PCLK 17 106 #define LSP0_I2C5_WCLK 18 107 #define LSP0_SSP0_PCLK 19 108 #define LSP0_SSP0_WCLK 20 109 #define LSP0_SSP1_PCLK 21 110 #define LSP0_SSP1_WCLK 22 111 #define LSP0_USIM_PCLK 23 112 #define LSP0_USIM_WCLK 24 113 #define LSP0_GPIO_PCLK 25 114 #define LSP0_GPIO_WCLK 26 115 #define LSP0_I2C3_PCLK 27 116 #define LSP0_I2C3_WCLK 28 117 118 #define LSP0_NR_CLKS 29 119 120 121 #define LSP1_UART4_PCLK 1 122 #define LSP1_UART4_WCLK 2 123 #define LSP1_UART5_PCLK 3 124 #define LSP1_UART5_WCLK 4 125 #define LSP1_PWM_PCLK 5 126 #define LSP1_PWM_WCLK 6 127 #define LSP1_I2C2_PCLK 7 128 #define LSP1_I2C2_WCLK 8 129 #define LSP1_SSP2_PCLK 9 130 #define LSP1_SSP2_WCLK 10 131 #define LSP1_SSP3_PCLK 11 132 #define LSP1_SSP3_WCLK 12 133 #define LSP1_SSP4_PCLK 13 134 #define LSP1_SSP4_WCLK 14 135 #define LSP1_USIM1_PCLK 15 136 #define LSP1_USIM1_WCLK 16 137 138 #define LSP1_NR_CLKS 17 139 140 141 #define AUDIO_I2S0_WCLK 1 142 #define AUDIO_I2S0_PCLK 2 143 #define AUDIO_I2S1_WCLK 3 144 #define AUDIO_I2S1_PCLK 4 145 #define AUDIO_I2S2_WCLK 5 146 #define AUDIO_I2S2_PCLK 6 147 #define AUDIO_I2S3_WCLK 7 148 #define AUDIO_I2S3_PCLK 8 149 #define AUDIO_I2C0_WCLK 9 150 #define AUDIO_I2C0_PCLK 10 151 #define AUDIO_SPDIF0_WCLK 11 152 #define AUDIO_SPDIF0_PCLK 12 153 #define AUDIO_SPDIF1_WCLK 13 154 #define AUDIO_SPDIF1_PCLK 14 155 #define AUDIO_TIMER_WCLK 15 156 #define AUDIO_TIMER_PCLK 16 157 #define AUDIO_TDM_WCLK 17 158 #define AUDIO_TDM_PCLK 18 159 #define AUDIO_TS_PCLK 19 160 #define I2S0_WCLK_MUX 20 161 #define I2S1_WCLK_MUX 21 162 #define I2S2_WCLK_MUX 22 163 #define I2S3_WCLK_MUX 23 164 165 #define AUDIO_NR_CLKS 24 166 167 #endif 168