1 /**
2 * Freecale 85xx and 86xx Global Utilties register set
3 *
4 * Authors: Jeff Brown
5 * Timur Tabi <timur@freescale.com>
6 *
7 * Copyright 2004,2007,2012 Freescale Semiconductor, Inc
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15 #ifndef __FSL_GUTS_H__
16 #define __FSL_GUTS_H__
17
18 #include <linux/types.h>
19 #include <linux/io.h>
20
21 /**
22 * Global Utility Registers.
23 *
24 * Not all registers defined in this structure are available on all chips, so
25 * you are expected to know whether a given register actually exists on your
26 * chip before you access it.
27 *
28 * Also, some registers are similar on different chips but have slightly
29 * different names. In these cases, one name is chosen to avoid extraneous
30 * #ifdefs.
31 */
32 struct ccsr_guts {
33 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
34 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
35 u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and
36 * Control Register
37 */
38 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
39 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
40 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
41 u8 res018[0x20 - 0x18];
42 u32 porcir; /* 0x.0020 - POR Configuration Information
43 * Register
44 */
45 u8 res024[0x30 - 0x24];
46 u32 gpiocr; /* 0x.0030 - GPIO Control Register */
47 u8 res034[0x40 - 0x34];
48 u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data
49 * Register
50 */
51 u8 res044[0x50 - 0x44];
52 u32 gpindr; /* 0x.0050 - General-Purpose Input Data
53 * Register
54 */
55 u8 res054[0x60 - 0x54];
56 u32 pmuxcr; /* 0x.0060 - Alternate Function Signal
57 * Multiplex Control
58 */
59 u32 pmuxcr2; /* 0x.0064 - Alternate function signal
60 * multiplex control 2
61 */
62 u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
63 u8 res06c[0x70 - 0x6c];
64 u32 devdisr; /* 0x.0070 - Device Disable Control */
65 #define CCSR_GUTS_DEVDISR_TB1 0x00001000
66 #define CCSR_GUTS_DEVDISR_TB0 0x00004000
67 u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
68 u8 res078[0x7c - 0x78];
69 u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control
70 * Register
71 */
72 u32 powmgtcsr; /* 0x.0080 - Power Management Status and
73 * Control Register
74 */
75 u32 pmrccr; /* 0x.0084 - Power Management Reset Counter
76 * Configuration Register
77 */
78 u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter
79 * Configuration Register
80 */
81 u32 pmcdr; /* 0x.008c - 4Power management clock disable
82 * register
83 */
84 u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
85 u32 rstrscr; /* 0x.0094 - Reset Request Status and
86 * Control Register
87 */
88 u32 ectrstcr; /* 0x.0098 - Exception reset control register */
89 u32 autorstsr; /* 0x.009c - Automatic reset status register */
90 u32 pvr; /* 0x.00a0 - Processor Version Register */
91 u32 svr; /* 0x.00a4 - System Version Register */
92 u8 res0a8[0xb0 - 0xa8];
93 u32 rstcr; /* 0x.00b0 - Reset Control Register */
94 u8 res0b4[0xc0 - 0xb4];
95 u32 iovselsr; /* 0x.00c0 - I/O voltage select status register
96 Called 'elbcvselcr' on 86xx SOCs */
97 u8 res0c4[0x100 - 0xc4];
98 u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
99 There are 16 registers */
100 u8 res140[0x224 - 0x140];
101 u32 iodelay1; /* 0x.0224 - IO delay control register 1 */
102 u32 iodelay2; /* 0x.0228 - IO delay control register 2 */
103 u8 res22c[0x604 - 0x22c];
104 u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
105 u8 res608[0x800 - 0x608];
106 u32 clkdvdr; /* 0x.0800 - Clock Divide Register */
107 u8 res804[0x900 - 0x804];
108 u32 ircr; /* 0x.0900 - Infrared Control Register */
109 u8 res904[0x908 - 0x904];
110 u32 dmacr; /* 0x.0908 - DMA Control Register */
111 u8 res90c[0x914 - 0x90c];
112 u32 elbccr; /* 0x.0914 - eLBC Control Register */
113 u8 res918[0xb20 - 0x918];
114 u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
115 u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
116 u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
117 u8 resb2c[0xe00 - 0xb2c];
118 u32 clkocr; /* 0x.0e00 - Clock Out Select Register */
119 u8 rese04[0xe10 - 0xe04];
120 u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
121 u8 rese14[0xe20 - 0xe14];
122 u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
123 u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override
124 * register
125 */
126 u8 rese28[0xf04 - 0xe28];
127 u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
128 u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
129 u8 resf0c[0xf2c - 0xf0c];
130 u32 itcr; /* 0x.0f2c - Internal transaction control
131 * register
132 */
133 u8 resf30[0xf40 - 0xf30];
134 u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
135 u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
136 } __attribute__ ((packed));
137
138 u32 fsl_guts_get_svr(void);
139
140 /* Alternate function signal multiplex control */
141 #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
142
143 #ifdef CONFIG_PPC_86xx
144
145 #define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
146 #define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */
147
148 /*
149 * Set the DMACR register in the GUTS
150 *
151 * The DMACR register determines the source of initiated transfers for each
152 * channel on each DMA controller. Rather than have a bunch of repetitive
153 * macros for the bit patterns, we just have a function that calculates
154 * them.
155 *
156 * guts: Pointer to GUTS structure
157 * co: The DMA controller (0 or 1)
158 * ch: The channel on the DMA controller (0, 1, 2, or 3)
159 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
160 */
guts_set_dmacr(struct ccsr_guts __iomem * guts,unsigned int co,unsigned int ch,unsigned int device)161 static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
162 unsigned int co, unsigned int ch, unsigned int device)
163 {
164 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
165
166 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
167 }
168
169 #define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000
170 #define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */
171 #define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */
172 #define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */
173 #define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */
174 #define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */
175 #define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */
176 #define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */
177 #define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */
178 #define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */
179 #define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */
180 #define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */
181 #define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008
182 #define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004
183 #define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002
184 #define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001
185
186 /*
187 * Set the DMA external control bits in the GUTS
188 *
189 * The DMA external control bits in the PMUXCR are only meaningful for
190 * channels 0 and 3. Any other channels are ignored.
191 *
192 * guts: Pointer to GUTS structure
193 * co: The DMA controller (0 or 1)
194 * ch: The channel on the DMA controller (0, 1, 2, or 3)
195 * value: the new value for the bit (0 or 1)
196 */
guts_set_pmuxcr_dma(struct ccsr_guts __iomem * guts,unsigned int co,unsigned int ch,unsigned int value)197 static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
198 unsigned int co, unsigned int ch, unsigned int value)
199 {
200 if ((ch == 0) || (ch == 3)) {
201 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
202
203 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
204 }
205 }
206
207 #define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000
208 #define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000
209 #define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000
210 #define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
211 #define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000
212 #define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
213 (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
214 #define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16
215 #define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000
216 #define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
217 #define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF
218 #define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
219
220 #endif
221
222 struct ccsr_rcpm_v1 {
223 u8 res0000[4];
224 __be32 cdozsr; /* 0x0004 Core Doze Status Register */
225 u8 res0008[4];
226 __be32 cdozcr; /* 0x000c Core Doze Control Register */
227 u8 res0010[4];
228 __be32 cnapsr; /* 0x0014 Core Nap Status Register */
229 u8 res0018[4];
230 __be32 cnapcr; /* 0x001c Core Nap Control Register */
231 u8 res0020[4];
232 __be32 cdozpsr; /* 0x0024 Core Doze Previous Status Register */
233 u8 res0028[4];
234 __be32 cnappsr; /* 0x002c Core Nap Previous Status Register */
235 u8 res0030[4];
236 __be32 cwaitsr; /* 0x0034 Core Wait Status Register */
237 u8 res0038[4];
238 __be32 cwdtdsr; /* 0x003c Core Watchdog Detect Status Register */
239 __be32 powmgtcsr; /* 0x0040 PM Control&Status Register */
240 #define RCPM_POWMGTCSR_SLP 0x00020000
241 u8 res0044[12];
242 __be32 ippdexpcr; /* 0x0050 IP Powerdown Exception Control Register */
243 u8 res0054[16];
244 __be32 cpmimr; /* 0x0064 Core PM IRQ Mask Register */
245 u8 res0068[4];
246 __be32 cpmcimr; /* 0x006c Core PM Critical IRQ Mask Register */
247 u8 res0070[4];
248 __be32 cpmmcmr; /* 0x0074 Core PM Machine Check Mask Register */
249 u8 res0078[4];
250 __be32 cpmnmimr; /* 0x007c Core PM NMI Mask Register */
251 u8 res0080[4];
252 __be32 ctbenr; /* 0x0084 Core Time Base Enable Register */
253 u8 res0088[4];
254 __be32 ctbckselr; /* 0x008c Core Time Base Clock Select Register */
255 u8 res0090[4];
256 __be32 ctbhltcr; /* 0x0094 Core Time Base Halt Control Register */
257 u8 res0098[4];
258 __be32 cmcpmaskcr; /* 0x00a4 Core Machine Check Mask Register */
259 };
260
261 struct ccsr_rcpm_v2 {
262 u8 res_00[12];
263 __be32 tph10sr0; /* Thread PH10 Status Register */
264 u8 res_10[12];
265 __be32 tph10setr0; /* Thread PH10 Set Control Register */
266 u8 res_20[12];
267 __be32 tph10clrr0; /* Thread PH10 Clear Control Register */
268 u8 res_30[12];
269 __be32 tph10psr0; /* Thread PH10 Previous Status Register */
270 u8 res_40[12];
271 __be32 twaitsr0; /* Thread Wait Status Register */
272 u8 res_50[96];
273 __be32 pcph15sr; /* Physical Core PH15 Status Register */
274 __be32 pcph15setr; /* Physical Core PH15 Set Control Register */
275 __be32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
276 __be32 pcph15psr; /* Physical Core PH15 Prev Status Register */
277 u8 res_c0[16];
278 __be32 pcph20sr; /* Physical Core PH20 Status Register */
279 __be32 pcph20setr; /* Physical Core PH20 Set Control Register */
280 __be32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
281 __be32 pcph20psr; /* Physical Core PH20 Prev Status Register */
282 __be32 pcpw20sr; /* Physical Core PW20 Status Register */
283 u8 res_e0[12];
284 __be32 pcph30sr; /* Physical Core PH30 Status Register */
285 __be32 pcph30setr; /* Physical Core PH30 Set Control Register */
286 __be32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
287 __be32 pcph30psr; /* Physical Core PH30 Prev Status Register */
288 u8 res_100[32];
289 __be32 ippwrgatecr; /* IP Power Gating Control Register */
290 u8 res_124[12];
291 __be32 powmgtcsr; /* Power Management Control & Status Reg */
292 #define RCPM_POWMGTCSR_LPM20_RQ 0x00100000
293 #define RCPM_POWMGTCSR_LPM20_ST 0x00000200
294 #define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100
295 u8 res_134[12];
296 __be32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
297 u8 res_150[12];
298 __be32 tpmimr0; /* Thread PM Interrupt Mask Reg */
299 u8 res_160[12];
300 __be32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
301 u8 res_170[12];
302 __be32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
303 u8 res_180[12];
304 __be32 tpmnmimr0; /* Thread PM NMI Mask Reg */
305 u8 res_190[12];
306 __be32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
307 __be32 pctbenr; /* Physical Core Time Base Enable Reg */
308 __be32 pctbclkselr; /* Physical Core Time Base Clock Select */
309 __be32 tbclkdivr; /* Time Base Clock Divider Register */
310 u8 res_1ac[4];
311 __be32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
312 __be32 clpcl10sr; /* Cluster PCL10 Status Register */
313 __be32 clpcl10setr; /* Cluster PCL30 Set Control Register */
314 __be32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
315 __be32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
316 __be32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
317 __be32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
318 __be32 cdpwroksetr; /* Core Domain Power OK Set Register */
319 __be32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
320 __be32 cdpwrensr; /* Core Domain Power Enable Status Register */
321 __be32 cddslsr; /* Core Domain Deep Sleep Status Register */
322 u8 res_1e8[8];
323 __be32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
324 u8 res_300[3568];
325 };
326
327 #endif
328