1 /*
2 * include/linux/mfd/wm831x/core.h -- Core interface for WM831x
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15 #ifndef __MFD_WM831X_CORE_H__
16 #define __MFD_WM831X_CORE_H__
17
18 #include <linux/completion.h>
19 #include <linux/interrupt.h>
20 #include <linux/irqdomain.h>
21 #include <linux/list.h>
22 #include <linux/regmap.h>
23 #include <linux/mfd/wm831x/auxadc.h>
24 #include <linux/mfd/wm831x/pdata.h>
25 #include <linux/of.h>
26
27 /*
28 * Register values.
29 */
30 #define WM831X_RESET_ID 0x00
31 #define WM831X_REVISION 0x01
32 #define WM831X_PARENT_ID 0x4000
33 #define WM831X_SYSVDD_CONTROL 0x4001
34 #define WM831X_THERMAL_MONITORING 0x4002
35 #define WM831X_POWER_STATE 0x4003
36 #define WM831X_WATCHDOG 0x4004
37 #define WM831X_ON_PIN_CONTROL 0x4005
38 #define WM831X_RESET_CONTROL 0x4006
39 #define WM831X_CONTROL_INTERFACE 0x4007
40 #define WM831X_SECURITY_KEY 0x4008
41 #define WM831X_SOFTWARE_SCRATCH 0x4009
42 #define WM831X_OTP_CONTROL 0x400A
43 #define WM831X_GPIO_LEVEL 0x400C
44 #define WM831X_SYSTEM_STATUS 0x400D
45 #define WM831X_ON_SOURCE 0x400E
46 #define WM831X_OFF_SOURCE 0x400F
47 #define WM831X_SYSTEM_INTERRUPTS 0x4010
48 #define WM831X_INTERRUPT_STATUS_1 0x4011
49 #define WM831X_INTERRUPT_STATUS_2 0x4012
50 #define WM831X_INTERRUPT_STATUS_3 0x4013
51 #define WM831X_INTERRUPT_STATUS_4 0x4014
52 #define WM831X_INTERRUPT_STATUS_5 0x4015
53 #define WM831X_IRQ_CONFIG 0x4017
54 #define WM831X_SYSTEM_INTERRUPTS_MASK 0x4018
55 #define WM831X_INTERRUPT_STATUS_1_MASK 0x4019
56 #define WM831X_INTERRUPT_STATUS_2_MASK 0x401A
57 #define WM831X_INTERRUPT_STATUS_3_MASK 0x401B
58 #define WM831X_INTERRUPT_STATUS_4_MASK 0x401C
59 #define WM831X_INTERRUPT_STATUS_5_MASK 0x401D
60 #define WM831X_RTC_WRITE_COUNTER 0x4020
61 #define WM831X_RTC_TIME_1 0x4021
62 #define WM831X_RTC_TIME_2 0x4022
63 #define WM831X_RTC_ALARM_1 0x4023
64 #define WM831X_RTC_ALARM_2 0x4024
65 #define WM831X_RTC_CONTROL 0x4025
66 #define WM831X_RTC_TRIM 0x4026
67 #define WM831X_TOUCH_CONTROL_1 0x4028
68 #define WM831X_TOUCH_CONTROL_2 0x4029
69 #define WM831X_TOUCH_DATA_X 0x402A
70 #define WM831X_TOUCH_DATA_Y 0x402B
71 #define WM831X_TOUCH_DATA_Z 0x402C
72 #define WM831X_AUXADC_DATA 0x402D
73 #define WM831X_AUXADC_CONTROL 0x402E
74 #define WM831X_AUXADC_SOURCE 0x402F
75 #define WM831X_COMPARATOR_CONTROL 0x4030
76 #define WM831X_COMPARATOR_1 0x4031
77 #define WM831X_COMPARATOR_2 0x4032
78 #define WM831X_COMPARATOR_3 0x4033
79 #define WM831X_COMPARATOR_4 0x4034
80 #define WM831X_GPIO1_CONTROL 0x4038
81 #define WM831X_GPIO2_CONTROL 0x4039
82 #define WM831X_GPIO3_CONTROL 0x403A
83 #define WM831X_GPIO4_CONTROL 0x403B
84 #define WM831X_GPIO5_CONTROL 0x403C
85 #define WM831X_GPIO6_CONTROL 0x403D
86 #define WM831X_GPIO7_CONTROL 0x403E
87 #define WM831X_GPIO8_CONTROL 0x403F
88 #define WM831X_GPIO9_CONTROL 0x4040
89 #define WM831X_GPIO10_CONTROL 0x4041
90 #define WM831X_GPIO11_CONTROL 0x4042
91 #define WM831X_GPIO12_CONTROL 0x4043
92 #define WM831X_GPIO13_CONTROL 0x4044
93 #define WM831X_GPIO14_CONTROL 0x4045
94 #define WM831X_GPIO15_CONTROL 0x4046
95 #define WM831X_GPIO16_CONTROL 0x4047
96 #define WM831X_CHARGER_CONTROL_1 0x4048
97 #define WM831X_CHARGER_CONTROL_2 0x4049
98 #define WM831X_CHARGER_STATUS 0x404A
99 #define WM831X_BACKUP_CHARGER_CONTROL 0x404B
100 #define WM831X_STATUS_LED_1 0x404C
101 #define WM831X_STATUS_LED_2 0x404D
102 #define WM831X_CURRENT_SINK_1 0x404E
103 #define WM831X_CURRENT_SINK_2 0x404F
104 #define WM831X_DCDC_ENABLE 0x4050
105 #define WM831X_LDO_ENABLE 0x4051
106 #define WM831X_DCDC_STATUS 0x4052
107 #define WM831X_LDO_STATUS 0x4053
108 #define WM831X_DCDC_UV_STATUS 0x4054
109 #define WM831X_LDO_UV_STATUS 0x4055
110 #define WM831X_DC1_CONTROL_1 0x4056
111 #define WM831X_DC1_CONTROL_2 0x4057
112 #define WM831X_DC1_ON_CONFIG 0x4058
113 #define WM831X_DC1_SLEEP_CONTROL 0x4059
114 #define WM831X_DC1_DVS_CONTROL 0x405A
115 #define WM831X_DC2_CONTROL_1 0x405B
116 #define WM831X_DC2_CONTROL_2 0x405C
117 #define WM831X_DC2_ON_CONFIG 0x405D
118 #define WM831X_DC2_SLEEP_CONTROL 0x405E
119 #define WM831X_DC2_DVS_CONTROL 0x405F
120 #define WM831X_DC3_CONTROL_1 0x4060
121 #define WM831X_DC3_CONTROL_2 0x4061
122 #define WM831X_DC3_ON_CONFIG 0x4062
123 #define WM831X_DC3_SLEEP_CONTROL 0x4063
124 #define WM831X_DC4_CONTROL 0x4064
125 #define WM831X_DC4_SLEEP_CONTROL 0x4065
126 #define WM832X_DC4_SLEEP_CONTROL 0x4067
127 #define WM831X_EPE1_CONTROL 0x4066
128 #define WM831X_EPE2_CONTROL 0x4067
129 #define WM831X_LDO1_CONTROL 0x4068
130 #define WM831X_LDO1_ON_CONTROL 0x4069
131 #define WM831X_LDO1_SLEEP_CONTROL 0x406A
132 #define WM831X_LDO2_CONTROL 0x406B
133 #define WM831X_LDO2_ON_CONTROL 0x406C
134 #define WM831X_LDO2_SLEEP_CONTROL 0x406D
135 #define WM831X_LDO3_CONTROL 0x406E
136 #define WM831X_LDO3_ON_CONTROL 0x406F
137 #define WM831X_LDO3_SLEEP_CONTROL 0x4070
138 #define WM831X_LDO4_CONTROL 0x4071
139 #define WM831X_LDO4_ON_CONTROL 0x4072
140 #define WM831X_LDO4_SLEEP_CONTROL 0x4073
141 #define WM831X_LDO5_CONTROL 0x4074
142 #define WM831X_LDO5_ON_CONTROL 0x4075
143 #define WM831X_LDO5_SLEEP_CONTROL 0x4076
144 #define WM831X_LDO6_CONTROL 0x4077
145 #define WM831X_LDO6_ON_CONTROL 0x4078
146 #define WM831X_LDO6_SLEEP_CONTROL 0x4079
147 #define WM831X_LDO7_CONTROL 0x407A
148 #define WM831X_LDO7_ON_CONTROL 0x407B
149 #define WM831X_LDO7_SLEEP_CONTROL 0x407C
150 #define WM831X_LDO8_CONTROL 0x407D
151 #define WM831X_LDO8_ON_CONTROL 0x407E
152 #define WM831X_LDO8_SLEEP_CONTROL 0x407F
153 #define WM831X_LDO9_CONTROL 0x4080
154 #define WM831X_LDO9_ON_CONTROL 0x4081
155 #define WM831X_LDO9_SLEEP_CONTROL 0x4082
156 #define WM831X_LDO10_CONTROL 0x4083
157 #define WM831X_LDO10_ON_CONTROL 0x4084
158 #define WM831X_LDO10_SLEEP_CONTROL 0x4085
159 #define WM831X_LDO11_ON_CONTROL 0x4087
160 #define WM831X_LDO11_SLEEP_CONTROL 0x4088
161 #define WM831X_POWER_GOOD_SOURCE_1 0x408E
162 #define WM831X_POWER_GOOD_SOURCE_2 0x408F
163 #define WM831X_CLOCK_CONTROL_1 0x4090
164 #define WM831X_CLOCK_CONTROL_2 0x4091
165 #define WM831X_FLL_CONTROL_1 0x4092
166 #define WM831X_FLL_CONTROL_2 0x4093
167 #define WM831X_FLL_CONTROL_3 0x4094
168 #define WM831X_FLL_CONTROL_4 0x4095
169 #define WM831X_FLL_CONTROL_5 0x4096
170 #define WM831X_UNIQUE_ID_1 0x7800
171 #define WM831X_UNIQUE_ID_2 0x7801
172 #define WM831X_UNIQUE_ID_3 0x7802
173 #define WM831X_UNIQUE_ID_4 0x7803
174 #define WM831X_UNIQUE_ID_5 0x7804
175 #define WM831X_UNIQUE_ID_6 0x7805
176 #define WM831X_UNIQUE_ID_7 0x7806
177 #define WM831X_UNIQUE_ID_8 0x7807
178 #define WM831X_FACTORY_OTP_ID 0x7808
179 #define WM831X_FACTORY_OTP_1 0x7809
180 #define WM831X_FACTORY_OTP_2 0x780A
181 #define WM831X_FACTORY_OTP_3 0x780B
182 #define WM831X_FACTORY_OTP_4 0x780C
183 #define WM831X_FACTORY_OTP_5 0x780D
184 #define WM831X_CUSTOMER_OTP_ID 0x7810
185 #define WM831X_DC1_OTP_CONTROL 0x7811
186 #define WM831X_DC2_OTP_CONTROL 0x7812
187 #define WM831X_DC3_OTP_CONTROL 0x7813
188 #define WM831X_LDO1_2_OTP_CONTROL 0x7814
189 #define WM831X_LDO3_4_OTP_CONTROL 0x7815
190 #define WM831X_LDO5_6_OTP_CONTROL 0x7816
191 #define WM831X_LDO7_8_OTP_CONTROL 0x7817
192 #define WM831X_LDO9_10_OTP_CONTROL 0x7818
193 #define WM831X_LDO11_EPE_CONTROL 0x7819
194 #define WM831X_GPIO1_OTP_CONTROL 0x781A
195 #define WM831X_GPIO2_OTP_CONTROL 0x781B
196 #define WM831X_GPIO3_OTP_CONTROL 0x781C
197 #define WM831X_GPIO4_OTP_CONTROL 0x781D
198 #define WM831X_GPIO5_OTP_CONTROL 0x781E
199 #define WM831X_GPIO6_OTP_CONTROL 0x781F
200 #define WM831X_DBE_CHECK_DATA 0x7827
201
202 /*
203 * R0 (0x00) - Reset ID
204 */
205 #define WM831X_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */
206 #define WM831X_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */
207 #define WM831X_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */
208
209 /*
210 * R1 (0x01) - Revision
211 */
212 #define WM831X_PARENT_REV_MASK 0xFF00 /* PARENT_REV - [15:8] */
213 #define WM831X_PARENT_REV_SHIFT 8 /* PARENT_REV - [15:8] */
214 #define WM831X_PARENT_REV_WIDTH 8 /* PARENT_REV - [15:8] */
215 #define WM831X_CHILD_REV_MASK 0x00FF /* CHILD_REV - [7:0] */
216 #define WM831X_CHILD_REV_SHIFT 0 /* CHILD_REV - [7:0] */
217 #define WM831X_CHILD_REV_WIDTH 8 /* CHILD_REV - [7:0] */
218
219 /*
220 * R16384 (0x4000) - Parent ID
221 */
222 #define WM831X_PARENT_ID_MASK 0xFFFF /* PARENT_ID - [15:0] */
223 #define WM831X_PARENT_ID_SHIFT 0 /* PARENT_ID - [15:0] */
224 #define WM831X_PARENT_ID_WIDTH 16 /* PARENT_ID - [15:0] */
225
226 /*
227 * R16389 (0x4005) - ON Pin Control
228 */
229 #define WM831X_ON_PIN_SECACT_MASK 0x0300 /* ON_PIN_SECACT - [9:8] */
230 #define WM831X_ON_PIN_SECACT_SHIFT 8 /* ON_PIN_SECACT - [9:8] */
231 #define WM831X_ON_PIN_SECACT_WIDTH 2 /* ON_PIN_SECACT - [9:8] */
232 #define WM831X_ON_PIN_PRIMACT_MASK 0x0030 /* ON_PIN_PRIMACT - [5:4] */
233 #define WM831X_ON_PIN_PRIMACT_SHIFT 4 /* ON_PIN_PRIMACT - [5:4] */
234 #define WM831X_ON_PIN_PRIMACT_WIDTH 2 /* ON_PIN_PRIMACT - [5:4] */
235 #define WM831X_ON_PIN_STS 0x0008 /* ON_PIN_STS */
236 #define WM831X_ON_PIN_STS_MASK 0x0008 /* ON_PIN_STS */
237 #define WM831X_ON_PIN_STS_SHIFT 3 /* ON_PIN_STS */
238 #define WM831X_ON_PIN_STS_WIDTH 1 /* ON_PIN_STS */
239 #define WM831X_ON_PIN_TO_MASK 0x0003 /* ON_PIN_TO - [1:0] */
240 #define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */
241 #define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */
242
243 /*
244 * R16528 (0x4090) - Clock Control 1
245 */
246 #define WM831X_CLKOUT_ENA 0x8000 /* CLKOUT_ENA */
247 #define WM831X_CLKOUT_ENA_MASK 0x8000 /* CLKOUT_ENA */
248 #define WM831X_CLKOUT_ENA_SHIFT 15 /* CLKOUT_ENA */
249 #define WM831X_CLKOUT_ENA_WIDTH 1 /* CLKOUT_ENA */
250 #define WM831X_CLKOUT_OD 0x2000 /* CLKOUT_OD */
251 #define WM831X_CLKOUT_OD_MASK 0x2000 /* CLKOUT_OD */
252 #define WM831X_CLKOUT_OD_SHIFT 13 /* CLKOUT_OD */
253 #define WM831X_CLKOUT_OD_WIDTH 1 /* CLKOUT_OD */
254 #define WM831X_CLKOUT_SLOT_MASK 0x0700 /* CLKOUT_SLOT - [10:8] */
255 #define WM831X_CLKOUT_SLOT_SHIFT 8 /* CLKOUT_SLOT - [10:8] */
256 #define WM831X_CLKOUT_SLOT_WIDTH 3 /* CLKOUT_SLOT - [10:8] */
257 #define WM831X_CLKOUT_SLPSLOT_MASK 0x0070 /* CLKOUT_SLPSLOT - [6:4] */
258 #define WM831X_CLKOUT_SLPSLOT_SHIFT 4 /* CLKOUT_SLPSLOT - [6:4] */
259 #define WM831X_CLKOUT_SLPSLOT_WIDTH 3 /* CLKOUT_SLPSLOT - [6:4] */
260 #define WM831X_CLKOUT_SRC 0x0001 /* CLKOUT_SRC */
261 #define WM831X_CLKOUT_SRC_MASK 0x0001 /* CLKOUT_SRC */
262 #define WM831X_CLKOUT_SRC_SHIFT 0 /* CLKOUT_SRC */
263 #define WM831X_CLKOUT_SRC_WIDTH 1 /* CLKOUT_SRC */
264
265 /*
266 * R16529 (0x4091) - Clock Control 2
267 */
268 #define WM831X_XTAL_INH 0x8000 /* XTAL_INH */
269 #define WM831X_XTAL_INH_MASK 0x8000 /* XTAL_INH */
270 #define WM831X_XTAL_INH_SHIFT 15 /* XTAL_INH */
271 #define WM831X_XTAL_INH_WIDTH 1 /* XTAL_INH */
272 #define WM831X_XTAL_ENA 0x2000 /* XTAL_ENA */
273 #define WM831X_XTAL_ENA_MASK 0x2000 /* XTAL_ENA */
274 #define WM831X_XTAL_ENA_SHIFT 13 /* XTAL_ENA */
275 #define WM831X_XTAL_ENA_WIDTH 1 /* XTAL_ENA */
276 #define WM831X_XTAL_BKUPENA 0x1000 /* XTAL_BKUPENA */
277 #define WM831X_XTAL_BKUPENA_MASK 0x1000 /* XTAL_BKUPENA */
278 #define WM831X_XTAL_BKUPENA_SHIFT 12 /* XTAL_BKUPENA */
279 #define WM831X_XTAL_BKUPENA_WIDTH 1 /* XTAL_BKUPENA */
280 #define WM831X_FLL_AUTO 0x0080 /* FLL_AUTO */
281 #define WM831X_FLL_AUTO_MASK 0x0080 /* FLL_AUTO */
282 #define WM831X_FLL_AUTO_SHIFT 7 /* FLL_AUTO */
283 #define WM831X_FLL_AUTO_WIDTH 1 /* FLL_AUTO */
284 #define WM831X_FLL_AUTO_FREQ_MASK 0x0007 /* FLL_AUTO_FREQ - [2:0] */
285 #define WM831X_FLL_AUTO_FREQ_SHIFT 0 /* FLL_AUTO_FREQ - [2:0] */
286 #define WM831X_FLL_AUTO_FREQ_WIDTH 3 /* FLL_AUTO_FREQ - [2:0] */
287
288 /*
289 * R16530 (0x4092) - FLL Control 1
290 */
291 #define WM831X_FLL_FRAC 0x0004 /* FLL_FRAC */
292 #define WM831X_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */
293 #define WM831X_FLL_FRAC_SHIFT 2 /* FLL_FRAC */
294 #define WM831X_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
295 #define WM831X_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */
296 #define WM831X_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */
297 #define WM831X_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */
298 #define WM831X_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */
299 #define WM831X_FLL_ENA 0x0001 /* FLL_ENA */
300 #define WM831X_FLL_ENA_MASK 0x0001 /* FLL_ENA */
301 #define WM831X_FLL_ENA_SHIFT 0 /* FLL_ENA */
302 #define WM831X_FLL_ENA_WIDTH 1 /* FLL_ENA */
303
304 /*
305 * R16531 (0x4093) - FLL Control 2
306 */
307 #define WM831X_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */
308 #define WM831X_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */
309 #define WM831X_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */
310 #define WM831X_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */
311 #define WM831X_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */
312 #define WM831X_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */
313 #define WM831X_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
314 #define WM831X_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
315 #define WM831X_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
316
317 /*
318 * R16532 (0x4094) - FLL Control 3
319 */
320 #define WM831X_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
321 #define WM831X_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
322 #define WM831X_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
323
324 /*
325 * R16533 (0x4095) - FLL Control 4
326 */
327 #define WM831X_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
328 #define WM831X_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
329 #define WM831X_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
330 #define WM831X_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */
331 #define WM831X_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */
332 #define WM831X_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */
333
334 /*
335 * R16534 (0x4096) - FLL Control 5
336 */
337 #define WM831X_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */
338 #define WM831X_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */
339 #define WM831X_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */
340 #define WM831X_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */
341 #define WM831X_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */
342 #define WM831X_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */
343
344 struct regulator_dev;
345 struct irq_domain;
346
347 #define WM831X_NUM_IRQ_REGS 5
348 #define WM831X_NUM_GPIO_REGS 16
349
350 enum wm831x_parent {
351 WM8310 = 0x8310,
352 WM8311 = 0x8311,
353 WM8312 = 0x8312,
354 WM8320 = 0x8320,
355 WM8321 = 0x8321,
356 WM8325 = 0x8325,
357 WM8326 = 0x8326,
358 };
359
360 struct wm831x;
361
362 typedef int (*wm831x_auxadc_read_fn)(struct wm831x *wm831x,
363 enum wm831x_auxadc input);
364
365 struct wm831x {
366 struct mutex io_lock;
367
368 struct device *dev;
369
370 struct regmap *regmap;
371
372 struct wm831x_pdata pdata;
373 enum wm831x_parent type;
374
375 int irq; /* Our chip IRQ */
376 struct mutex irq_lock;
377 struct irq_domain *irq_domain;
378 int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */
379 int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
380
381 bool soft_shutdown;
382
383 /* Chip revision based flags */
384 unsigned has_gpio_ena:1; /* Has GPIO enable bit */
385 unsigned has_cs_sts:1; /* Has current sink status bit */
386 unsigned charger_irq_wake:1; /* Are charger IRQs a wake source? */
387
388 int num_gpio;
389
390 /* Used by the interrupt controller code to post writes */
391 int gpio_update[WM831X_NUM_GPIO_REGS];
392 bool gpio_level_high[WM831X_NUM_GPIO_REGS];
393 bool gpio_level_low[WM831X_NUM_GPIO_REGS];
394
395 struct mutex auxadc_lock;
396 struct list_head auxadc_pending;
397 u16 auxadc_active;
398 wm831x_auxadc_read_fn auxadc_read;
399
400 /* The WM831x has a security key blocking access to certain
401 * registers. The mutex is taken by the accessors for locking
402 * and unlocking the security key, locked is used to fail
403 * writes if the lock is held.
404 */
405 struct mutex key_lock;
406 unsigned int locked:1;
407 };
408
409 /* Device I/O API */
410 int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg);
411 int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg,
412 unsigned short val);
413 void wm831x_reg_lock(struct wm831x *wm831x);
414 int wm831x_reg_unlock(struct wm831x *wm831x);
415 int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
416 unsigned short mask, unsigned short val);
417 int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
418 int count, u16 *buf);
419
420 int wm831x_device_init(struct wm831x *wm831x, int irq);
421 void wm831x_device_exit(struct wm831x *wm831x);
422 int wm831x_device_suspend(struct wm831x *wm831x);
423 void wm831x_device_shutdown(struct wm831x *wm831x);
424 int wm831x_irq_init(struct wm831x *wm831x, int irq);
425 void wm831x_irq_exit(struct wm831x *wm831x);
426 void wm831x_auxadc_init(struct wm831x *wm831x);
427
wm831x_irq(struct wm831x * wm831x,int irq)428 static inline int wm831x_irq(struct wm831x *wm831x, int irq)
429 {
430 return irq_create_mapping(wm831x->irq_domain, irq);
431 }
432
433 extern struct regmap_config wm831x_regmap_config;
434
435 extern const struct of_device_id wm831x_of_match[];
436
437 #endif
438