1 /*
2 * Support for the xscale frame buffer.
3 *
4 * Author: Jean-Frederic Clere
5 * Created: Sep 22, 2003
6 * Copyright: jfclere@sinix.net
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/fb.h>
14 #include <mach/regs-lcd.h>
15
16 /*
17 * Supported LCD connections
18 *
19 * bits 0 - 3: for LCD panel type:
20 *
21 * STN - for passive matrix
22 * DSTN - for dual scan passive matrix
23 * TFT - for active matrix
24 *
25 * bits 4 - 9 : for bus width
26 * bits 10-17 : for AC Bias Pin Frequency
27 * bit 18 : for output enable polarity
28 * bit 19 : for pixel clock edge
29 * bit 20 : for output pixel format when base is RGBT16
30 */
31 #define LCD_CONN_TYPE(_x) ((_x) & 0x0f)
32 #define LCD_CONN_WIDTH(_x) (((_x) >> 4) & 0x1f)
33
34 #define LCD_TYPE_MASK 0xf
35 #define LCD_TYPE_UNKNOWN 0
36 #define LCD_TYPE_MONO_STN 1
37 #define LCD_TYPE_MONO_DSTN 2
38 #define LCD_TYPE_COLOR_STN 3
39 #define LCD_TYPE_COLOR_DSTN 4
40 #define LCD_TYPE_COLOR_TFT 5
41 #define LCD_TYPE_SMART_PANEL 6
42 #define LCD_TYPE_MAX 7
43
44 #define LCD_MONO_STN_4BPP ((4 << 4) | LCD_TYPE_MONO_STN)
45 #define LCD_MONO_STN_8BPP ((8 << 4) | LCD_TYPE_MONO_STN)
46 #define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN)
47 #define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN)
48 #define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN)
49 #define LCD_COLOR_TFT_8BPP ((8 << 4) | LCD_TYPE_COLOR_TFT)
50 #define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT)
51 #define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT)
52 #define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL)
53 #define LCD_SMART_PANEL_16BPP ((16 << 4) | LCD_TYPE_SMART_PANEL)
54 #define LCD_SMART_PANEL_18BPP ((18 << 4) | LCD_TYPE_SMART_PANEL)
55
56 #define LCD_AC_BIAS_FREQ(x) (((x) & 0xff) << 10)
57 #define LCD_BIAS_ACTIVE_HIGH (0 << 18)
58 #define LCD_BIAS_ACTIVE_LOW (1 << 18)
59 #define LCD_PCLK_EDGE_RISE (0 << 19)
60 #define LCD_PCLK_EDGE_FALL (1 << 19)
61 #define LCD_ALTERNATE_MAPPING (1 << 20)
62
63 /*
64 * This structure describes the machine which we are running on.
65 * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
66 * of linux/drivers/video/pxafb.c
67 */
68 struct pxafb_mode_info {
69 u_long pixclock;
70
71 u_short xres;
72 u_short yres;
73
74 u_char bpp;
75 u_int cmap_greyscale:1,
76 depth:8,
77 transparency:1,
78 unused:22;
79
80 /* Parallel Mode Timing */
81 u_char hsync_len;
82 u_char left_margin;
83 u_char right_margin;
84
85 u_char vsync_len;
86 u_char upper_margin;
87 u_char lower_margin;
88 u_char sync;
89
90 /* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
91 * Note:
92 * 1. all parameters in nanosecond (ns)
93 * 2. a0cs{rd,wr}_set_hld are controlled by the same register bits
94 * in pxa27x and pxa3xx, initialize them to the same value or
95 * the larger one will be used
96 * 3. same to {rd,wr}_pulse_width
97 *
98 * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity
99 * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0
100 * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD
101 */
102 unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
103 unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
104 unsigned wr_pulse_width; /* L_PCLK_WR pulse width */
105 unsigned rd_pulse_width; /* L_FCLK_RD pulse width */
106 unsigned cmd_inh_time; /* Command Inhibit time between two writes */
107 unsigned op_hold_time; /* Output Hold time from L_FCLK_RD negation */
108 };
109
110 struct pxafb_mach_info {
111 struct pxafb_mode_info *modes;
112 unsigned int num_modes;
113
114 unsigned int lcd_conn;
115 unsigned long video_mem_size;
116
117 u_int fixed_modes:1,
118 cmap_inverse:1,
119 cmap_static:1,
120 acceleration_enabled:1,
121 unused:28;
122
123 /* The following should be defined in LCCR0
124 * LCCR0_Act or LCCR0_Pas Active or Passive
125 * LCCR0_Sngl or LCCR0_Dual Single/Dual panel
126 * LCCR0_Mono or LCCR0_Color Mono/Color
127 * LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
128 * LCCR0_DMADel(Tcpu) (optional) DMA request delay
129 *
130 * The following should not be defined in LCCR0:
131 * LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
132 * LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
133 */
134 u_int lccr0;
135 /* The following should be defined in LCCR3
136 * LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity
137 * LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
138 * LCCR3_Acb(X) AB Bias pin frequency
139 * LCCR3_DPC (optional) Double Pixel Clock mode (untested)
140 *
141 * The following should not be defined in LCCR3
142 * LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
143 */
144 u_int lccr3;
145 /* The following should be defined in LCCR4
146 * LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
147 *
148 * All other bits in LCCR4 should be left alone.
149 */
150 u_int lccr4;
151 void (*pxafb_backlight_power)(int);
152 void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
153 void (*smart_update)(struct fb_info *);
154 };
155
156 void pxa_set_fb_info(struct device *, struct pxafb_mach_info *);
157 unsigned long pxafb_get_hsync_time(struct device *dev);
158
159 #ifdef CONFIG_FB_PXA_SMARTPANEL
160 extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
161 extern int pxafb_smart_flush(struct fb_info *info);
162 #else
pxafb_smart_queue(struct fb_info * info,uint16_t * cmds,int n)163 static inline int pxafb_smart_queue(struct fb_info *info,
164 uint16_t *cmds, int n)
165 {
166 return 0;
167 }
168
pxafb_smart_flush(struct fb_info * info)169 static inline int pxafb_smart_flush(struct fb_info *info)
170 {
171 return 0;
172 }
173 #endif
174