1 /* QLogic qed NIC Driver
2  * Copyright (c) 2015-2016  QLogic Corporation
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and /or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef _COMMON_HSI_H
34 #define _COMMON_HSI_H
35 
36 #include <linux/types.h>
37 #include <asm/byteorder.h>
38 #include <linux/bitops.h>
39 #include <linux/slab.h>
40 
41 /* dma_addr_t manip */
42 #define PTR_LO(x)		((u32)(((uintptr_t)(x)) & 0xffffffff))
43 #define PTR_HI(x)		((u32)((((uintptr_t)(x)) >> 16) >> 16))
44 #define DMA_LO_LE(x)		cpu_to_le32(lower_32_bits(x))
45 #define DMA_HI_LE(x)		cpu_to_le32(upper_32_bits(x))
46 #define DMA_REGPAIR_LE(x, val)	do { \
47 					(x).hi = DMA_HI_LE((val)); \
48 					(x).lo = DMA_LO_LE((val)); \
49 				} while (0)
50 
51 #define HILO_GEN(hi, lo, type)		((((type)(hi)) << 32) + (lo))
52 #define HILO_64(hi, lo) \
53 	HILO_GEN(le32_to_cpu(hi), le32_to_cpu(lo), u64)
54 #define HILO_64_REGPAIR(regpair) ({ \
55 	typeof(regpair) __regpair = (regpair); \
56 	HILO_64(__regpair.hi, __regpair.lo); })
57 #define HILO_DMA_REGPAIR(regpair)	((dma_addr_t)HILO_64_REGPAIR(regpair))
58 
59 #ifndef __COMMON_HSI__
60 #define __COMMON_HSI__
61 
62 /********************************/
63 /* PROTOCOL COMMON FW CONSTANTS */
64 /********************************/
65 
66 #define X_FINAL_CLEANUP_AGG_INT			1
67 
68 #define EVENT_RING_PAGE_SIZE_BYTES		4096
69 
70 #define NUM_OF_GLOBAL_QUEUES			128
71 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE	64
72 
73 #define ISCSI_CDU_TASK_SEG_TYPE			0
74 #define FCOE_CDU_TASK_SEG_TYPE			0
75 #define RDMA_CDU_TASK_SEG_TYPE			1
76 
77 #define FW_ASSERT_GENERAL_ATTN_IDX		32
78 
79 #define MAX_PINNED_CCFC				32
80 
81 /* Queue Zone sizes in bytes */
82 #define TSTORM_QZONE_SIZE	8
83 #define MSTORM_QZONE_SIZE	16
84 #define USTORM_QZONE_SIZE	8
85 #define XSTORM_QZONE_SIZE	8
86 #define YSTORM_QZONE_SIZE	0
87 #define PSTORM_QZONE_SIZE	0
88 
89 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG		7
90 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT	16
91 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE	48
92 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD	112
93 
94 /********************************/
95 /* CORE (LIGHT L2) FW CONSTANTS */
96 /********************************/
97 
98 #define CORE_LL2_MAX_RAMROD_PER_CON	8
99 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES	4096
100 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES	4096
101 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES	4096
102 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS	1
103 
104 #define CORE_LL2_TX_MAX_BDS_PER_PACKET	12
105 
106 #define CORE_SPQE_PAGE_SIZE_BYTES	4096
107 
108 #define MAX_NUM_LL2_RX_QUEUES		48
109 #define MAX_NUM_LL2_TX_STATS_COUNTERS	48
110 
111 #define FW_MAJOR_VERSION	8
112 #define FW_MINOR_VERSION        37
113 #define FW_REVISION_VERSION     2
114 #define FW_ENGINEERING_VERSION	0
115 
116 /***********************/
117 /* COMMON HW CONSTANTS */
118 /***********************/
119 
120 /* PCI functions */
121 #define MAX_NUM_PORTS_K2	(4)
122 #define MAX_NUM_PORTS_BB	(2)
123 #define MAX_NUM_PORTS		(MAX_NUM_PORTS_K2)
124 
125 #define MAX_NUM_PFS_K2		(16)
126 #define MAX_NUM_PFS_BB		(8)
127 #define MAX_NUM_PFS		(MAX_NUM_PFS_K2)
128 #define MAX_NUM_OF_PFS_IN_CHIP	(16) /* On both engines */
129 
130 #define MAX_NUM_VFS_K2	(192)
131 #define MAX_NUM_VFS_BB	(120)
132 #define MAX_NUM_VFS	(MAX_NUM_VFS_K2)
133 
134 #define MAX_NUM_FUNCTIONS_BB	(MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
135 #define MAX_NUM_FUNCTIONS	(MAX_NUM_PFS + MAX_NUM_VFS)
136 
137 #define MAX_FUNCTION_NUMBER_BB	(MAX_NUM_PFS + MAX_NUM_VFS_BB)
138 #define MAX_FUNCTION_NUMBER	(MAX_NUM_PFS + MAX_NUM_VFS)
139 
140 #define MAX_NUM_VPORTS_K2	(208)
141 #define MAX_NUM_VPORTS_BB	(160)
142 #define MAX_NUM_VPORTS		(MAX_NUM_VPORTS_K2)
143 
144 #define MAX_NUM_L2_QUEUES_K2	(320)
145 #define MAX_NUM_L2_QUEUES_BB	(256)
146 #define MAX_NUM_L2_QUEUES	(MAX_NUM_L2_QUEUES_K2)
147 
148 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
149 #define NUM_PHYS_TCS_4PORT_K2	(4)
150 #define NUM_OF_PHYS_TCS		(8)
151 #define PURE_LB_TC		NUM_OF_PHYS_TCS
152 #define NUM_TCS_4PORT_K2	(NUM_PHYS_TCS_4PORT_K2 + 1)
153 #define NUM_OF_TCS		(NUM_OF_PHYS_TCS + 1)
154 
155 /* CIDs */
156 #define NUM_OF_CONNECTION_TYPES_E4	(8)
157 #define NUM_OF_LCIDS			(320)
158 #define NUM_OF_LTIDS			(320)
159 
160 /* Global PXP windows (GTT) */
161 #define NUM_OF_GTT		19
162 #define GTT_DWORD_SIZE_BITS	10
163 #define GTT_BYTE_SIZE_BITS	(GTT_DWORD_SIZE_BITS + 2)
164 #define GTT_DWORD_SIZE		BIT(GTT_DWORD_SIZE_BITS)
165 
166 /* Tools Version */
167 #define TOOLS_VERSION	10
168 
169 /*****************/
170 /* CDU CONSTANTS */
171 /*****************/
172 
173 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT			(17)
174 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK			(0x1ffff)
175 
176 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT		(12)
177 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK		(0xfff)
178 
179 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT			(0)
180 #define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT	(1)
181 #define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE			(2)
182 #define CDU_CONTEXT_VALIDATION_CFG_USE_REGION			(3)
183 #define CDU_CONTEXT_VALIDATION_CFG_USE_CID			(4)
184 #define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE			(5)
185 
186 /*****************/
187 /* DQ CONSTANTS  */
188 /*****************/
189 
190 /* DEMS */
191 #define DQ_DEMS_LEGACY			0
192 #define DQ_DEMS_TOE_MORE_TO_SEND	3
193 #define DQ_DEMS_TOE_LOCAL_ADV_WND	4
194 #define DQ_DEMS_ROCE_CQ_CONS		7
195 
196 /* XCM agg val selection (HW) */
197 #define DQ_XCM_AGG_VAL_SEL_WORD2	0
198 #define DQ_XCM_AGG_VAL_SEL_WORD3	1
199 #define DQ_XCM_AGG_VAL_SEL_WORD4	2
200 #define DQ_XCM_AGG_VAL_SEL_WORD5	3
201 #define DQ_XCM_AGG_VAL_SEL_REG3		4
202 #define DQ_XCM_AGG_VAL_SEL_REG4		5
203 #define DQ_XCM_AGG_VAL_SEL_REG5		6
204 #define DQ_XCM_AGG_VAL_SEL_REG6		7
205 
206 /* XCM agg val selection (FW) */
207 #define	DQ_XCM_CORE_TX_BD_CONS_CMD		DQ_XCM_AGG_VAL_SEL_WORD3
208 #define	DQ_XCM_CORE_TX_BD_PROD_CMD		DQ_XCM_AGG_VAL_SEL_WORD4
209 #define	DQ_XCM_CORE_SPQ_PROD_CMD		DQ_XCM_AGG_VAL_SEL_WORD4
210 #define	DQ_XCM_ETH_EDPM_NUM_BDS_CMD		DQ_XCM_AGG_VAL_SEL_WORD2
211 #define	DQ_XCM_ETH_TX_BD_CONS_CMD		DQ_XCM_AGG_VAL_SEL_WORD3
212 #define	DQ_XCM_ETH_TX_BD_PROD_CMD		DQ_XCM_AGG_VAL_SEL_WORD4
213 #define	DQ_XCM_ETH_GO_TO_BD_CONS_CMD		DQ_XCM_AGG_VAL_SEL_WORD5
214 #define DQ_XCM_FCOE_SQ_CONS_CMD			DQ_XCM_AGG_VAL_SEL_WORD3
215 #define DQ_XCM_FCOE_SQ_PROD_CMD			DQ_XCM_AGG_VAL_SEL_WORD4
216 #define DQ_XCM_FCOE_X_FERQ_PROD_CMD		DQ_XCM_AGG_VAL_SEL_WORD5
217 #define DQ_XCM_ISCSI_SQ_CONS_CMD		DQ_XCM_AGG_VAL_SEL_WORD3
218 #define DQ_XCM_ISCSI_SQ_PROD_CMD		DQ_XCM_AGG_VAL_SEL_WORD4
219 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD	DQ_XCM_AGG_VAL_SEL_REG3
220 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD		DQ_XCM_AGG_VAL_SEL_REG6
221 #define DQ_XCM_ROCE_SQ_PROD_CMD			DQ_XCM_AGG_VAL_SEL_WORD4
222 #define DQ_XCM_TOE_TX_BD_PROD_CMD		DQ_XCM_AGG_VAL_SEL_WORD4
223 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD		DQ_XCM_AGG_VAL_SEL_REG3
224 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD	DQ_XCM_AGG_VAL_SEL_REG4
225 
226 /* UCM agg val selection (HW) */
227 #define	DQ_UCM_AGG_VAL_SEL_WORD0	0
228 #define	DQ_UCM_AGG_VAL_SEL_WORD1	1
229 #define	DQ_UCM_AGG_VAL_SEL_WORD2	2
230 #define	DQ_UCM_AGG_VAL_SEL_WORD3	3
231 #define	DQ_UCM_AGG_VAL_SEL_REG0		4
232 #define	DQ_UCM_AGG_VAL_SEL_REG1		5
233 #define	DQ_UCM_AGG_VAL_SEL_REG2		6
234 #define	DQ_UCM_AGG_VAL_SEL_REG3		7
235 
236 /* UCM agg val selection (FW) */
237 #define DQ_UCM_ETH_PMD_TX_CONS_CMD	DQ_UCM_AGG_VAL_SEL_WORD2
238 #define DQ_UCM_ETH_PMD_RX_CONS_CMD	DQ_UCM_AGG_VAL_SEL_WORD3
239 #define DQ_UCM_ROCE_CQ_CONS_CMD		DQ_UCM_AGG_VAL_SEL_REG0
240 #define DQ_UCM_ROCE_CQ_PROD_CMD		DQ_UCM_AGG_VAL_SEL_REG2
241 
242 /* TCM agg val selection (HW) */
243 #define	DQ_TCM_AGG_VAL_SEL_WORD0	0
244 #define	DQ_TCM_AGG_VAL_SEL_WORD1	1
245 #define	DQ_TCM_AGG_VAL_SEL_WORD2	2
246 #define	DQ_TCM_AGG_VAL_SEL_WORD3	3
247 #define	DQ_TCM_AGG_VAL_SEL_REG1		4
248 #define	DQ_TCM_AGG_VAL_SEL_REG2		5
249 #define	DQ_TCM_AGG_VAL_SEL_REG6		6
250 #define	DQ_TCM_AGG_VAL_SEL_REG9		7
251 
252 /* TCM agg val selection (FW) */
253 #define DQ_TCM_L2B_BD_PROD_CMD \
254 	DQ_TCM_AGG_VAL_SEL_WORD1
255 #define DQ_TCM_ROCE_RQ_PROD_CMD	\
256 	DQ_TCM_AGG_VAL_SEL_WORD0
257 
258 /* XCM agg counter flag selection (HW) */
259 #define	DQ_XCM_AGG_FLG_SHIFT_BIT14	0
260 #define	DQ_XCM_AGG_FLG_SHIFT_BIT15	1
261 #define	DQ_XCM_AGG_FLG_SHIFT_CF12	2
262 #define	DQ_XCM_AGG_FLG_SHIFT_CF13	3
263 #define	DQ_XCM_AGG_FLG_SHIFT_CF18	4
264 #define	DQ_XCM_AGG_FLG_SHIFT_CF19	5
265 #define	DQ_XCM_AGG_FLG_SHIFT_CF22	6
266 #define	DQ_XCM_AGG_FLG_SHIFT_CF23	7
267 
268 /* XCM agg counter flag selection (FW) */
269 #define DQ_XCM_CORE_DQ_CF_CMD			BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
270 #define DQ_XCM_CORE_TERMINATE_CMD		BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
271 #define DQ_XCM_CORE_SLOW_PATH_CMD		BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
272 #define DQ_XCM_ETH_DQ_CF_CMD			BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
273 #define DQ_XCM_ETH_TERMINATE_CMD		BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
274 #define DQ_XCM_ETH_SLOW_PATH_CMD		BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
275 #define DQ_XCM_ETH_TPH_EN_CMD			BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
276 #define DQ_XCM_FCOE_SLOW_PATH_CMD		BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
277 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD		BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
278 #define DQ_XCM_ISCSI_SLOW_PATH_CMD		BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
279 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD	BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
280 #define DQ_XCM_TOE_DQ_FLUSH_CMD			BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
281 #define DQ_XCM_TOE_SLOW_PATH_CMD		BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
282 
283 /* UCM agg counter flag selection (HW) */
284 #define	DQ_UCM_AGG_FLG_SHIFT_CF0	0
285 #define	DQ_UCM_AGG_FLG_SHIFT_CF1	1
286 #define	DQ_UCM_AGG_FLG_SHIFT_CF3	2
287 #define	DQ_UCM_AGG_FLG_SHIFT_CF4	3
288 #define	DQ_UCM_AGG_FLG_SHIFT_CF5	4
289 #define	DQ_UCM_AGG_FLG_SHIFT_CF6	5
290 #define	DQ_UCM_AGG_FLG_SHIFT_RULE0EN	6
291 #define	DQ_UCM_AGG_FLG_SHIFT_RULE1EN	7
292 
293 /* UCM agg counter flag selection (FW) */
294 #define DQ_UCM_ETH_PMD_TX_ARM_CMD	BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
295 #define DQ_UCM_ETH_PMD_RX_ARM_CMD	BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
296 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD	BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
297 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD	BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
298 #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD	BIT(DQ_UCM_AGG_FLG_SHIFT_CF3)
299 #define DQ_UCM_TOE_SLOW_PATH_CF_CMD	BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
300 #define DQ_UCM_TOE_DQ_CF_CMD		BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
301 
302 /* TCM agg counter flag selection (HW) */
303 #define DQ_TCM_AGG_FLG_SHIFT_CF0	0
304 #define DQ_TCM_AGG_FLG_SHIFT_CF1	1
305 #define DQ_TCM_AGG_FLG_SHIFT_CF2	2
306 #define DQ_TCM_AGG_FLG_SHIFT_CF3	3
307 #define DQ_TCM_AGG_FLG_SHIFT_CF4	4
308 #define DQ_TCM_AGG_FLG_SHIFT_CF5	5
309 #define DQ_TCM_AGG_FLG_SHIFT_CF6	6
310 #define DQ_TCM_AGG_FLG_SHIFT_CF7	7
311 /* TCM agg counter flag selection (FW) */
312 #define DQ_TCM_FCOE_FLUSH_Q0_CMD	BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
313 #define DQ_TCM_FCOE_DUMMY_TIMER_CMD	BIT(DQ_TCM_AGG_FLG_SHIFT_CF2)
314 #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD	BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
315 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD	BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
316 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD	BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
317 #define DQ_TCM_TOE_FLUSH_Q0_CMD		BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
318 #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD	BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
319 #define DQ_TCM_IWARP_POST_RQ_CF_CMD	BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
320 
321 /* PWM address mapping */
322 #define DQ_PWM_OFFSET_DPM_BASE		0x0
323 #define DQ_PWM_OFFSET_DPM_END		0x27
324 #define DQ_PWM_OFFSET_XCM16_BASE	0x40
325 #define DQ_PWM_OFFSET_XCM32_BASE	0x44
326 #define DQ_PWM_OFFSET_UCM16_BASE	0x48
327 #define DQ_PWM_OFFSET_UCM32_BASE	0x4C
328 #define DQ_PWM_OFFSET_UCM16_4		0x50
329 #define DQ_PWM_OFFSET_TCM16_BASE	0x58
330 #define DQ_PWM_OFFSET_TCM32_BASE	0x5C
331 #define DQ_PWM_OFFSET_XCM_FLAGS		0x68
332 #define DQ_PWM_OFFSET_UCM_FLAGS		0x69
333 #define DQ_PWM_OFFSET_TCM_FLAGS		0x6B
334 
335 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD		(DQ_PWM_OFFSET_XCM16_BASE + 2)
336 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT	(DQ_PWM_OFFSET_UCM32_BASE)
337 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT	(DQ_PWM_OFFSET_UCM16_4)
338 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT	(DQ_PWM_OFFSET_UCM16_BASE + 2)
339 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS	(DQ_PWM_OFFSET_UCM_FLAGS)
340 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD		(DQ_PWM_OFFSET_TCM16_BASE + 1)
341 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD		(DQ_PWM_OFFSET_TCM16_BASE + 3)
342 
343 #define	DQ_REGION_SHIFT			(12)
344 
345 /* DPM */
346 #define	DQ_DPM_WQE_BUFF_SIZE		(320)
347 
348 /* Conn type ranges */
349 #define	DQ_CONN_TYPE_RANGE_SHIFT	(4)
350 
351 /*****************/
352 /* QM CONSTANTS  */
353 /*****************/
354 
355 /* Number of TX queues in the QM */
356 #define MAX_QM_TX_QUEUES_K2	512
357 #define MAX_QM_TX_QUEUES_BB	448
358 #define MAX_QM_TX_QUEUES	MAX_QM_TX_QUEUES_K2
359 
360 /* Number of Other queues in the QM */
361 #define MAX_QM_OTHER_QUEUES_BB	64
362 #define MAX_QM_OTHER_QUEUES_K2	128
363 #define MAX_QM_OTHER_QUEUES	MAX_QM_OTHER_QUEUES_K2
364 
365 /* Number of queues in a PF queue group */
366 #define QM_PF_QUEUE_GROUP_SIZE	8
367 
368 /* The size of a single queue element in bytes */
369 #define QM_PQ_ELEMENT_SIZE	4
370 
371 /* Base number of Tx PQs in the CM PQ representation.
372  * Should be used when storing PQ IDs in CM PQ registers and context.
373  */
374 #define CM_TX_PQ_BASE		0x200
375 
376 /* Number of global Vport/QCN rate limiters */
377 #define MAX_QM_GLOBAL_RLS	256
378 
379 /* QM registers data */
380 #define QM_LINE_CRD_REG_WIDTH		16
381 #define QM_LINE_CRD_REG_SIGN_BIT	BIT((QM_LINE_CRD_REG_WIDTH - 1))
382 #define QM_BYTE_CRD_REG_WIDTH		24
383 #define QM_BYTE_CRD_REG_SIGN_BIT	BIT((QM_BYTE_CRD_REG_WIDTH - 1))
384 #define QM_WFQ_CRD_REG_WIDTH		32
385 #define QM_WFQ_CRD_REG_SIGN_BIT		BIT((QM_WFQ_CRD_REG_WIDTH - 1))
386 #define QM_RL_CRD_REG_WIDTH		32
387 #define QM_RL_CRD_REG_SIGN_BIT		BIT((QM_RL_CRD_REG_WIDTH - 1))
388 
389 /*****************/
390 /* CAU CONSTANTS */
391 /*****************/
392 
393 #define CAU_FSM_ETH_RX  0
394 #define CAU_FSM_ETH_TX  1
395 
396 /* Number of Protocol Indices per Status Block */
397 #define PIS_PER_SB_E4	12
398 
399 #define CAU_HC_STOPPED_STATE	3
400 #define CAU_HC_DISABLE_STATE	4
401 #define CAU_HC_ENABLE_STATE	0
402 
403 /*****************/
404 /* IGU CONSTANTS */
405 /*****************/
406 
407 #define MAX_SB_PER_PATH_K2	(368)
408 #define MAX_SB_PER_PATH_BB	(288)
409 #define MAX_TOT_SB_PER_PATH \
410 	MAX_SB_PER_PATH_K2
411 
412 #define MAX_SB_PER_PF_MIMD	129
413 #define MAX_SB_PER_PF_SIMD	64
414 #define MAX_SB_PER_VF		64
415 
416 /* Memory addresses on the BAR for the IGU Sub Block */
417 #define IGU_MEM_BASE			0x0000
418 
419 #define IGU_MEM_MSIX_BASE		0x0000
420 #define IGU_MEM_MSIX_UPPER		0x0101
421 #define IGU_MEM_MSIX_RESERVED_UPPER	0x01ff
422 
423 #define IGU_MEM_PBA_MSIX_BASE		0x0200
424 #define IGU_MEM_PBA_MSIX_UPPER		0x0202
425 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER	0x03ff
426 
427 #define IGU_CMD_INT_ACK_BASE		0x0400
428 #define IGU_CMD_INT_ACK_UPPER		(IGU_CMD_INT_ACK_BASE +	\
429 					 MAX_TOT_SB_PER_PATH - 1)
430 #define IGU_CMD_INT_ACK_RESERVED_UPPER	0x05ff
431 
432 #define IGU_CMD_ATTN_BIT_UPD_UPPER	0x05f0
433 #define IGU_CMD_ATTN_BIT_SET_UPPER	0x05f1
434 #define IGU_CMD_ATTN_BIT_CLR_UPPER	0x05f2
435 
436 #define IGU_REG_SISR_MDPC_WMASK_UPPER		0x05f3
437 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER	0x05f4
438 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER	0x05f5
439 #define IGU_REG_SISR_MDPC_WOMASK_UPPER		0x05f6
440 
441 #define IGU_CMD_PROD_UPD_BASE			0x0600
442 #define IGU_CMD_PROD_UPD_UPPER			(IGU_CMD_PROD_UPD_BASE +\
443 						 MAX_TOT_SB_PER_PATH - 1)
444 #define IGU_CMD_PROD_UPD_RESERVED_UPPER		0x07ff
445 
446 /*****************/
447 /* PXP CONSTANTS */
448 /*****************/
449 
450 /* Bars for Blocks */
451 #define PXP_BAR_GRC	0
452 #define PXP_BAR_TSDM	0
453 #define PXP_BAR_USDM	0
454 #define PXP_BAR_XSDM	0
455 #define PXP_BAR_MSDM	0
456 #define PXP_BAR_YSDM	0
457 #define PXP_BAR_PSDM	0
458 #define PXP_BAR_IGU	0
459 #define PXP_BAR_DQ	1
460 
461 /* PTT and GTT */
462 #define PXP_PER_PF_ENTRY_SIZE		8
463 #define PXP_NUM_GLOBAL_WINDOWS		243
464 #define PXP_GLOBAL_ENTRY_SIZE		4
465 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH	4
466 #define PXP_PF_WINDOW_ADMIN_START	0
467 #define PXP_PF_WINDOW_ADMIN_LENGTH	0x1000
468 #define PXP_PF_WINDOW_ADMIN_END		(PXP_PF_WINDOW_ADMIN_START + \
469 					 PXP_PF_WINDOW_ADMIN_LENGTH - 1)
470 #define PXP_PF_WINDOW_ADMIN_PER_PF_START	0
471 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH	(PXP_NUM_PF_WINDOWS * \
472 						 PXP_PER_PF_ENTRY_SIZE)
473 #define PXP_PF_WINDOW_ADMIN_PER_PF_END	(PXP_PF_WINDOW_ADMIN_PER_PF_START + \
474 					 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1)
475 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START	0x200
476 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH	(PXP_NUM_GLOBAL_WINDOWS * \
477 						 PXP_GLOBAL_ENTRY_SIZE)
478 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \
479 		(PXP_PF_WINDOW_ADMIN_GLOBAL_START + \
480 		 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1)
481 #define PXP_PF_GLOBAL_PRETEND_ADDR	0x1f0
482 #define PXP_PF_ME_OPAQUE_MASK_ADDR	0xf4
483 #define PXP_PF_ME_OPAQUE_ADDR		0x1f8
484 #define PXP_PF_ME_CONCRETE_ADDR		0x1fc
485 
486 #define PXP_NUM_PF_WINDOWS	12
487 #define PXP_EXTERNAL_BAR_PF_WINDOW_START	0x1000
488 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM		PXP_NUM_PF_WINDOWS
489 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE	0x1000
490 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \
491 	(PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \
492 	 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE)
493 #define PXP_EXTERNAL_BAR_PF_WINDOW_END \
494 	(PXP_EXTERNAL_BAR_PF_WINDOW_START + \
495 	 PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1)
496 
497 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \
498 	(PXP_EXTERNAL_BAR_PF_WINDOW_END + 1)
499 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM		PXP_NUM_GLOBAL_WINDOWS
500 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE	0x1000
501 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \
502 	(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \
503 	 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE)
504 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \
505 	(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \
506 	 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
507 
508 /* PF BAR */
509 #define PXP_BAR0_START_GRC		0x0000
510 #define PXP_BAR0_GRC_LENGTH		0x1C00000
511 #define PXP_BAR0_END_GRC		(PXP_BAR0_START_GRC + \
512 					 PXP_BAR0_GRC_LENGTH - 1)
513 
514 #define PXP_BAR0_START_IGU		0x1C00000
515 #define PXP_BAR0_IGU_LENGTH		0x10000
516 #define PXP_BAR0_END_IGU		(PXP_BAR0_START_IGU + \
517 					 PXP_BAR0_IGU_LENGTH - 1)
518 
519 #define PXP_BAR0_START_TSDM		0x1C80000
520 #define PXP_BAR0_SDM_LENGTH		0x40000
521 #define PXP_BAR0_SDM_RESERVED_LENGTH	0x40000
522 #define PXP_BAR0_END_TSDM		(PXP_BAR0_START_TSDM + \
523 					 PXP_BAR0_SDM_LENGTH - 1)
524 
525 #define PXP_BAR0_START_MSDM		0x1D00000
526 #define PXP_BAR0_END_MSDM		(PXP_BAR0_START_MSDM + \
527 					 PXP_BAR0_SDM_LENGTH - 1)
528 
529 #define PXP_BAR0_START_USDM		0x1D80000
530 #define PXP_BAR0_END_USDM		(PXP_BAR0_START_USDM + \
531 					 PXP_BAR0_SDM_LENGTH - 1)
532 
533 #define PXP_BAR0_START_XSDM		0x1E00000
534 #define PXP_BAR0_END_XSDM		(PXP_BAR0_START_XSDM + \
535 					 PXP_BAR0_SDM_LENGTH - 1)
536 
537 #define PXP_BAR0_START_YSDM		0x1E80000
538 #define PXP_BAR0_END_YSDM		(PXP_BAR0_START_YSDM + \
539 					 PXP_BAR0_SDM_LENGTH - 1)
540 
541 #define PXP_BAR0_START_PSDM		0x1F00000
542 #define PXP_BAR0_END_PSDM		(PXP_BAR0_START_PSDM + \
543 					 PXP_BAR0_SDM_LENGTH - 1)
544 
545 #define PXP_BAR0_FIRST_INVALID_ADDRESS	(PXP_BAR0_END_PSDM + 1)
546 
547 /* VF BAR */
548 #define PXP_VF_BAR0			0
549 
550 #define PXP_VF_BAR0_START_IGU		0
551 #define PXP_VF_BAR0_IGU_LENGTH		0x3000
552 #define PXP_VF_BAR0_END_IGU		(PXP_VF_BAR0_START_IGU + \
553 					 PXP_VF_BAR0_IGU_LENGTH - 1)
554 
555 #define PXP_VF_BAR0_START_DQ		0x3000
556 #define PXP_VF_BAR0_DQ_LENGTH		0x200
557 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET	0
558 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS	(PXP_VF_BAR0_START_DQ +	\
559 					 PXP_VF_BAR0_DQ_OPAQUE_OFFSET)
560 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS	(PXP_VF_BAR0_ME_OPAQUE_ADDRESS \
561 					 + 4)
562 #define PXP_VF_BAR0_END_DQ		(PXP_VF_BAR0_START_DQ +	\
563 					 PXP_VF_BAR0_DQ_LENGTH - 1)
564 
565 #define PXP_VF_BAR0_START_TSDM_ZONE_B	0x3200
566 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B	0x200
567 #define PXP_VF_BAR0_END_TSDM_ZONE_B	(PXP_VF_BAR0_START_TSDM_ZONE_B + \
568 					 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
569 
570 #define PXP_VF_BAR0_START_MSDM_ZONE_B	0x3400
571 #define PXP_VF_BAR0_END_MSDM_ZONE_B	(PXP_VF_BAR0_START_MSDM_ZONE_B + \
572 					 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
573 
574 #define PXP_VF_BAR0_START_USDM_ZONE_B	0x3600
575 #define PXP_VF_BAR0_END_USDM_ZONE_B	(PXP_VF_BAR0_START_USDM_ZONE_B + \
576 					 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
577 
578 #define PXP_VF_BAR0_START_XSDM_ZONE_B	0x3800
579 #define PXP_VF_BAR0_END_XSDM_ZONE_B	(PXP_VF_BAR0_START_XSDM_ZONE_B + \
580 					 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
581 
582 #define PXP_VF_BAR0_START_YSDM_ZONE_B	0x3a00
583 #define PXP_VF_BAR0_END_YSDM_ZONE_B	(PXP_VF_BAR0_START_YSDM_ZONE_B + \
584 					 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
585 
586 #define PXP_VF_BAR0_START_PSDM_ZONE_B	0x3c00
587 #define PXP_VF_BAR0_END_PSDM_ZONE_B	(PXP_VF_BAR0_START_PSDM_ZONE_B + \
588 					 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
589 
590 #define PXP_VF_BAR0_START_GRC		0x3E00
591 #define PXP_VF_BAR0_GRC_LENGTH		0x200
592 #define PXP_VF_BAR0_END_GRC		(PXP_VF_BAR0_START_GRC + \
593 					 PXP_VF_BAR0_GRC_LENGTH - 1)
594 
595 #define PXP_VF_BAR0_START_SDM_ZONE_A	0x4000
596 #define PXP_VF_BAR0_END_SDM_ZONE_A	0x10000
597 
598 #define PXP_VF_BAR0_START_IGU2		0x10000
599 #define PXP_VF_BAR0_IGU2_LENGTH		0xD000
600 #define PXP_VF_BAR0_END_IGU2		(PXP_VF_BAR0_START_IGU2 + \
601 					 PXP_VF_BAR0_IGU2_LENGTH - 1)
602 
603 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH	32
604 
605 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN	12
606 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER	1024
607 
608 /* ILT Records */
609 #define PXP_NUM_ILT_RECORDS_BB 7600
610 #define PXP_NUM_ILT_RECORDS_K2 11000
611 #define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
612 
613 /* Host Interface */
614 #define PXP_QUEUES_ZONE_MAX_NUM	320
615 
616 /*****************/
617 /* PRM CONSTANTS */
618 /*****************/
619 #define PRM_DMA_PAD_BYTES_NUM	2
620 
621 /*****************/
622 /* SDMs CONSTANTS  */
623 /*****************/
624 
625 #define SDM_OP_GEN_TRIG_NONE		0
626 #define SDM_OP_GEN_TRIG_WAKE_THREAD	1
627 #define SDM_OP_GEN_TRIG_AGG_INT		2
628 #define SDM_OP_GEN_TRIG_LOADER		4
629 #define SDM_OP_GEN_TRIG_INDICATE_ERROR  6
630 #define SDM_OP_GEN_TRIG_INC_ORDER_CNT   9
631 
632 /********************/
633 /* Completion types */
634 /********************/
635 
636 #define SDM_COMP_TYPE_NONE		0
637 #define SDM_COMP_TYPE_WAKE_THREAD	1
638 #define SDM_COMP_TYPE_AGG_INT		2
639 #define SDM_COMP_TYPE_CM		3
640 #define SDM_COMP_TYPE_LOADER		4
641 #define SDM_COMP_TYPE_PXP		5
642 #define SDM_COMP_TYPE_INDICATE_ERROR	6
643 #define SDM_COMP_TYPE_RELEASE_THREAD	7
644 #define SDM_COMP_TYPE_RAM		8
645 #define SDM_COMP_TYPE_INC_ORDER_CNT	9
646 
647 /*****************/
648 /* PBF CONSTANTS */
649 /*****************/
650 
651 /* Number of PBF command queue lines. Each line is 32B. */
652 #define PBF_MAX_CMD_LINES	3328
653 
654 /* Number of BTB blocks. Each block is 256B. */
655 #define BTB_MAX_BLOCKS		1440
656 
657 /*****************/
658 /* PRS CONSTANTS */
659 /*****************/
660 
661 #define PRS_GFT_CAM_LINES_NO_MATCH	31
662 
663 /* Interrupt coalescing TimeSet */
664 struct coalescing_timeset {
665 	u8 value;
666 #define	COALESCING_TIMESET_TIMESET_MASK		0x7F
667 #define	COALESCING_TIMESET_TIMESET_SHIFT	0
668 #define	COALESCING_TIMESET_VALID_MASK		0x1
669 #define	COALESCING_TIMESET_VALID_SHIFT		7
670 };
671 
672 struct common_queue_zone {
673 	__le16 ring_drv_data_consumer;
674 	__le16 reserved;
675 };
676 
677 /* ETH Rx producers data */
678 struct eth_rx_prod_data {
679 	__le16 bd_prod;
680 	__le16 cqe_prod;
681 };
682 
683 struct tcp_ulp_connect_done_params {
684 	__le16 mss;
685 	u8 snd_wnd_scale;
686 	u8 flags;
687 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK		0x1
688 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT		0
689 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK	0x7F
690 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_SHIFT	1
691 };
692 
693 struct iscsi_connect_done_results {
694 	__le16 icid;
695 	__le16 conn_id;
696 	struct tcp_ulp_connect_done_params params;
697 };
698 
699 struct iscsi_eqe_data {
700 	__le16 icid;
701 	__le16 conn_id;
702 	__le16 reserved;
703 	u8 error_code;
704 	u8 error_pdu_opcode_reserved;
705 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK		0x3F
706 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT		0
707 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK	0x1
708 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT	 6
709 #define ISCSI_EQE_DATA_RESERVED0_MASK			0x1
710 #define ISCSI_EQE_DATA_RESERVED0_SHIFT			7
711 };
712 
713 /* Multi function mode */
714 enum mf_mode {
715 	ERROR_MODE /* Unsupported mode */,
716 	MF_OVLAN,
717 	MF_NPAR,
718 	MAX_MF_MODE
719 };
720 
721 /* Per-protocol connection types */
722 enum protocol_type {
723 	PROTOCOLID_ISCSI,
724 	PROTOCOLID_FCOE,
725 	PROTOCOLID_ROCE,
726 	PROTOCOLID_CORE,
727 	PROTOCOLID_ETH,
728 	PROTOCOLID_IWARP,
729 	PROTOCOLID_RESERVED0,
730 	PROTOCOLID_PREROCE,
731 	PROTOCOLID_COMMON,
732 	PROTOCOLID_RESERVED1,
733 	MAX_PROTOCOL_TYPE
734 };
735 
736 struct regpair {
737 	__le32 lo;
738 	__le32 hi;
739 };
740 
741 /* RoCE Destroy Event Data */
742 struct rdma_eqe_destroy_qp {
743 	__le32 cid;
744 	u8 reserved[4];
745 };
746 
747 /* RDMA Event Data Union */
748 union rdma_eqe_data {
749 	struct regpair async_handle;
750 	struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
751 };
752 
753 /* Ustorm Queue Zone */
754 struct ustorm_eth_queue_zone {
755 	struct coalescing_timeset int_coalescing_timeset;
756 	u8 reserved[3];
757 };
758 
759 struct ustorm_queue_zone {
760 	struct ustorm_eth_queue_zone eth;
761 	struct common_queue_zone common;
762 };
763 
764 /* Status block structure */
765 struct cau_pi_entry {
766 	__le32 prod;
767 #define CAU_PI_ENTRY_PROD_VAL_MASK	0xFFFF
768 #define CAU_PI_ENTRY_PROD_VAL_SHIFT	0
769 #define CAU_PI_ENTRY_PI_TIMESET_MASK	0x7F
770 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT	16
771 #define CAU_PI_ENTRY_FSM_SEL_MASK	0x1
772 #define CAU_PI_ENTRY_FSM_SEL_SHIFT	23
773 #define CAU_PI_ENTRY_RESERVED_MASK	0xFF
774 #define CAU_PI_ENTRY_RESERVED_SHIFT	24
775 };
776 
777 /* Status block structure */
778 struct cau_sb_entry {
779 	__le32 data;
780 #define CAU_SB_ENTRY_SB_PROD_MASK	0xFFFFFF
781 #define CAU_SB_ENTRY_SB_PROD_SHIFT	0
782 #define CAU_SB_ENTRY_STATE0_MASK	0xF
783 #define CAU_SB_ENTRY_STATE0_SHIFT	24
784 #define CAU_SB_ENTRY_STATE1_MASK	0xF
785 #define CAU_SB_ENTRY_STATE1_SHIFT	28
786 	__le32 params;
787 #define CAU_SB_ENTRY_SB_TIMESET0_MASK	0x7F
788 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT	0
789 #define CAU_SB_ENTRY_SB_TIMESET1_MASK	0x7F
790 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT	7
791 #define CAU_SB_ENTRY_TIMER_RES0_MASK	0x3
792 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT	14
793 #define CAU_SB_ENTRY_TIMER_RES1_MASK	0x3
794 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT	16
795 #define CAU_SB_ENTRY_VF_NUMBER_MASK	0xFF
796 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT	18
797 #define CAU_SB_ENTRY_VF_VALID_MASK	0x1
798 #define CAU_SB_ENTRY_VF_VALID_SHIFT	26
799 #define CAU_SB_ENTRY_PF_NUMBER_MASK	0xF
800 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT	27
801 #define CAU_SB_ENTRY_TPH_MASK		0x1
802 #define CAU_SB_ENTRY_TPH_SHIFT		31
803 };
804 
805 /* Igu cleanup bit values to distinguish between clean or producer consumer
806  * update.
807  */
808 enum command_type_bit {
809 	IGU_COMMAND_TYPE_NOP = 0,
810 	IGU_COMMAND_TYPE_SET = 1,
811 	MAX_COMMAND_TYPE_BIT
812 };
813 
814 /* Core doorbell data */
815 struct core_db_data {
816 	u8 params;
817 #define CORE_DB_DATA_DEST_MASK		0x3
818 #define CORE_DB_DATA_DEST_SHIFT		0
819 #define CORE_DB_DATA_AGG_CMD_MASK	0x3
820 #define CORE_DB_DATA_AGG_CMD_SHIFT	2
821 #define CORE_DB_DATA_BYPASS_EN_MASK	0x1
822 #define CORE_DB_DATA_BYPASS_EN_SHIFT	4
823 #define CORE_DB_DATA_RESERVED_MASK	0x1
824 #define CORE_DB_DATA_RESERVED_SHIFT	5
825 #define CORE_DB_DATA_AGG_VAL_SEL_MASK	0x3
826 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT	6
827 	u8 agg_flags;
828 	__le16 spq_prod;
829 };
830 
831 /* Enum of doorbell aggregative command selection */
832 enum db_agg_cmd_sel {
833 	DB_AGG_CMD_NOP,
834 	DB_AGG_CMD_SET,
835 	DB_AGG_CMD_ADD,
836 	DB_AGG_CMD_MAX,
837 	MAX_DB_AGG_CMD_SEL
838 };
839 
840 /* Enum of doorbell destination */
841 enum db_dest {
842 	DB_DEST_XCM,
843 	DB_DEST_UCM,
844 	DB_DEST_TCM,
845 	DB_NUM_DESTINATIONS,
846 	MAX_DB_DEST
847 };
848 
849 /* Enum of doorbell DPM types */
850 enum db_dpm_type {
851 	DPM_LEGACY,
852 	DPM_RDMA,
853 	DPM_L2_INLINE,
854 	DPM_L2_BD,
855 	MAX_DB_DPM_TYPE
856 };
857 
858 /* Structure for doorbell data, in L2 DPM mode, for 1st db in a DPM burst */
859 struct db_l2_dpm_data {
860 	__le16 icid;
861 	__le16 bd_prod;
862 	__le32 params;
863 #define DB_L2_DPM_DATA_SIZE_MASK	0x3F
864 #define DB_L2_DPM_DATA_SIZE_SHIFT	0
865 #define DB_L2_DPM_DATA_DPM_TYPE_MASK	0x3
866 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT	6
867 #define DB_L2_DPM_DATA_NUM_BDS_MASK	0xFF
868 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT	8
869 #define DB_L2_DPM_DATA_PKT_SIZE_MASK	0x7FF
870 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT	16
871 #define DB_L2_DPM_DATA_RESERVED0_MASK	0x1
872 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27
873 #define DB_L2_DPM_DATA_SGE_NUM_MASK	0x7
874 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT	28
875 #define DB_L2_DPM_DATA_GFS_SRC_EN_MASK	0x1
876 #define DB_L2_DPM_DATA_GFS_SRC_EN_SHIFT	31
877 };
878 
879 /* Structure for SGE in a DPM doorbell of type DPM_L2_BD */
880 struct db_l2_dpm_sge {
881 	struct regpair addr;
882 	__le16 nbytes;
883 	__le16 bitfields;
884 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK		0x1FF
885 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT	0
886 #define DB_L2_DPM_SGE_RESERVED0_MASK		0x3
887 #define DB_L2_DPM_SGE_RESERVED0_SHIFT		9
888 #define DB_L2_DPM_SGE_ST_VALID_MASK		0x1
889 #define DB_L2_DPM_SGE_ST_VALID_SHIFT		11
890 #define DB_L2_DPM_SGE_RESERVED1_MASK		0xF
891 #define DB_L2_DPM_SGE_RESERVED1_SHIFT		12
892 	__le32 reserved2;
893 };
894 
895 /* Structure for doorbell address, in legacy mode */
896 struct db_legacy_addr {
897 	__le32 addr;
898 #define DB_LEGACY_ADDR_RESERVED0_MASK	0x3
899 #define DB_LEGACY_ADDR_RESERVED0_SHIFT	0
900 #define DB_LEGACY_ADDR_DEMS_MASK	0x7
901 #define DB_LEGACY_ADDR_DEMS_SHIFT	2
902 #define DB_LEGACY_ADDR_ICID_MASK	0x7FFFFFF
903 #define DB_LEGACY_ADDR_ICID_SHIFT	5
904 };
905 
906 /* Structure for doorbell address, in PWM mode */
907 struct db_pwm_addr {
908 	__le32 addr;
909 #define DB_PWM_ADDR_RESERVED0_MASK	0x7
910 #define DB_PWM_ADDR_RESERVED0_SHIFT	0
911 #define DB_PWM_ADDR_OFFSET_MASK		0x7F
912 #define DB_PWM_ADDR_OFFSET_SHIFT	3
913 #define DB_PWM_ADDR_WID_MASK		0x3
914 #define DB_PWM_ADDR_WID_SHIFT		10
915 #define DB_PWM_ADDR_DPI_MASK		0xFFFF
916 #define DB_PWM_ADDR_DPI_SHIFT		12
917 #define DB_PWM_ADDR_RESERVED1_MASK	0xF
918 #define DB_PWM_ADDR_RESERVED1_SHIFT	28
919 };
920 
921 /* Parameters to RDMA firmware, passed in EDPM doorbell */
922 struct db_rdma_dpm_params {
923 	__le32 params;
924 #define DB_RDMA_DPM_PARAMS_SIZE_MASK			0x3F
925 #define DB_RDMA_DPM_PARAMS_SIZE_SHIFT			0
926 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK		0x3
927 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT		6
928 #define DB_RDMA_DPM_PARAMS_OPCODE_MASK			0xFF
929 #define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT			8
930 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK		0x7FF
931 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT		16
932 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK		0x1
933 #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT		27
934 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK		0x1
935 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT		28
936 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK			0x1
937 #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT			29
938 #define DB_RDMA_DPM_PARAMS_RESERVED1_MASK		0x1
939 #define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT		30
940 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK	0x1
941 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT	31
942 };
943 
944 /* Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a
945  * DPM burst.
946  */
947 struct db_rdma_dpm_data {
948 	__le16 icid;
949 	__le16 prod_val;
950 	struct db_rdma_dpm_params params;
951 };
952 
953 /* Igu interrupt command */
954 enum igu_int_cmd {
955 	IGU_INT_ENABLE	= 0,
956 	IGU_INT_DISABLE = 1,
957 	IGU_INT_NOP	= 2,
958 	IGU_INT_NOP2	= 3,
959 	MAX_IGU_INT_CMD
960 };
961 
962 /* IGU producer or consumer update command */
963 struct igu_prod_cons_update {
964 	__le32 sb_id_and_flags;
965 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK		0xFFFFFF
966 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT		0
967 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK		0x1
968 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT		24
969 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK		0x3
970 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT		25
971 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK	0x1
972 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT	27
973 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK		0x1
974 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT		28
975 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK		0x3
976 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT		29
977 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK		0x1
978 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT		31
979 	__le32 reserved1;
980 };
981 
982 /* Igu segments access for default status block only */
983 enum igu_seg_access {
984 	IGU_SEG_ACCESS_REG	= 0,
985 	IGU_SEG_ACCESS_ATTN	= 1,
986 	MAX_IGU_SEG_ACCESS
987 };
988 
989 /* Enumeration for L3 type field of parsing_and_err_flags.
990  * L3Type: 0 - unknown (not ip), 1 - Ipv4, 2 - Ipv6
991  * (This field can be filled according to the last-ethertype)
992  */
993 enum l3_type {
994 	e_l3_type_unknown,
995 	e_l3_type_ipv4,
996 	e_l3_type_ipv6,
997 	MAX_L3_TYPE
998 };
999 
1000 /* Enumeration for l4Protocol field of parsing_and_err_flags.
1001  * L4-protocol: 0 - none, 1 - TCP, 2 - UDP.
1002  * If the packet is IPv4 fragment, and its not the first fragment, the
1003  * protocol-type should be set to none.
1004  */
1005 enum l4_protocol {
1006 	e_l4_protocol_none,
1007 	e_l4_protocol_tcp,
1008 	e_l4_protocol_udp,
1009 	MAX_L4_PROTOCOL
1010 };
1011 
1012 /* Parsing and error flags field */
1013 struct parsing_and_err_flags {
1014 	__le16 flags;
1015 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK			0x3
1016 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT			0
1017 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK			0x3
1018 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT			2
1019 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK			0x1
1020 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT			4
1021 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK		0x1
1022 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT		5
1023 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK		0x1
1024 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT	6
1025 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK			0x1
1026 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT			7
1027 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK		0x1
1028 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT		8
1029 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK			0x1
1030 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT			9
1031 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK			0x1
1032 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT		10
1033 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK			0x1
1034 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT			11
1035 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK		0x1
1036 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT		12
1037 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK		0x1
1038 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT		13
1039 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK	0x1
1040 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT	14
1041 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK		0x1
1042 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT		15
1043 };
1044 
1045 /* Parsing error flags bitmap */
1046 struct parsing_err_flags {
1047 	__le16 flags;
1048 #define PARSING_ERR_FLAGS_MAC_ERROR_MASK				0x1
1049 #define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT				0
1050 #define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK				0x1
1051 #define PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT				1
1052 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK				0x1
1053 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT				2
1054 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK			0x1
1055 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT			3
1056 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK			0x1
1057 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT			4
1058 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK		0x1
1059 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT		5
1060 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK			0x1
1061 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT		6
1062 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK			0x1
1063 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT			7
1064 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK		0x1
1065 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT		8
1066 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK			0x1
1067 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT			9
1068 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK			0x1
1069 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT			10
1070 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK		0x1
1071 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT		11
1072 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK	0x1
1073 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT	12
1074 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK			0x1
1075 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT			13
1076 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK			0x1
1077 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT		14
1078 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK			0x1
1079 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT			15
1080 };
1081 
1082 /* Pb context */
1083 struct pb_context {
1084 	__le32 crc[4];
1085 };
1086 
1087 /* Concrete Function ID */
1088 struct pxp_concrete_fid {
1089 	__le16 fid;
1090 #define PXP_CONCRETE_FID_PFID_MASK	0xF
1091 #define PXP_CONCRETE_FID_PFID_SHIFT	0
1092 #define PXP_CONCRETE_FID_PORT_MASK	0x3
1093 #define PXP_CONCRETE_FID_PORT_SHIFT	4
1094 #define PXP_CONCRETE_FID_PATH_MASK	0x1
1095 #define PXP_CONCRETE_FID_PATH_SHIFT	6
1096 #define PXP_CONCRETE_FID_VFVALID_MASK	0x1
1097 #define PXP_CONCRETE_FID_VFVALID_SHIFT	7
1098 #define PXP_CONCRETE_FID_VFID_MASK	0xFF
1099 #define PXP_CONCRETE_FID_VFID_SHIFT	8
1100 };
1101 
1102 /* Concrete Function ID */
1103 struct pxp_pretend_concrete_fid {
1104 	__le16 fid;
1105 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK	0xF
1106 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT	0
1107 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK	0x7
1108 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT	4
1109 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK	0x1
1110 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT	7
1111 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK	0xFF
1112 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT	8
1113 };
1114 
1115 /* Function ID */
1116 union pxp_pretend_fid {
1117 	struct pxp_pretend_concrete_fid concrete_fid;
1118 	__le16 opaque_fid;
1119 };
1120 
1121 /* Pxp Pretend Command Register */
1122 struct pxp_pretend_cmd {
1123 	union pxp_pretend_fid fid;
1124 	__le16 control;
1125 #define PXP_PRETEND_CMD_PATH_MASK		0x1
1126 #define PXP_PRETEND_CMD_PATH_SHIFT		0
1127 #define PXP_PRETEND_CMD_USE_PORT_MASK		0x1
1128 #define PXP_PRETEND_CMD_USE_PORT_SHIFT		1
1129 #define PXP_PRETEND_CMD_PORT_MASK		0x3
1130 #define PXP_PRETEND_CMD_PORT_SHIFT		2
1131 #define PXP_PRETEND_CMD_RESERVED0_MASK		0xF
1132 #define PXP_PRETEND_CMD_RESERVED0_SHIFT		4
1133 #define PXP_PRETEND_CMD_RESERVED1_MASK		0xF
1134 #define PXP_PRETEND_CMD_RESERVED1_SHIFT		8
1135 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK	0x1
1136 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT	12
1137 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK	0x1
1138 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT	13
1139 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK	0x1
1140 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT	14
1141 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK	0x1
1142 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT	15
1143 };
1144 
1145 /* PTT Record in PXP Admin Window */
1146 struct pxp_ptt_entry {
1147 	__le32 offset;
1148 #define PXP_PTT_ENTRY_OFFSET_MASK	0x7FFFFF
1149 #define PXP_PTT_ENTRY_OFFSET_SHIFT	0
1150 #define PXP_PTT_ENTRY_RESERVED0_MASK	0x1FF
1151 #define PXP_PTT_ENTRY_RESERVED0_SHIFT	23
1152 	struct pxp_pretend_cmd pretend;
1153 };
1154 
1155 /* VF Zone A Permission Register */
1156 struct pxp_vf_zone_a_permission {
1157 	__le32 control;
1158 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK		0xFF
1159 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT		0
1160 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK		0x1
1161 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT		8
1162 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK		0x7F
1163 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT	9
1164 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK		0xFFFF
1165 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT	16
1166 };
1167 
1168 /* Rdif context */
1169 struct rdif_task_context {
1170 	__le32 initial_ref_tag;
1171 	__le16 app_tag_value;
1172 	__le16 app_tag_mask;
1173 	u8 flags0;
1174 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK		0x1
1175 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT		0
1176 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK	0x1
1177 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT	1
1178 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK		0x1
1179 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT		2
1180 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK	0x1
1181 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT	3
1182 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK		0x3
1183 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT		4
1184 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK			0x1
1185 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT		6
1186 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK	0x1
1187 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT	7
1188 	u8 partial_dif_data[7];
1189 	__le16 partial_crc_value;
1190 	__le16 partial_checksum_value;
1191 	__le32 offset_in_io;
1192 	__le16 flags1;
1193 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK			0x1
1194 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT			0
1195 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK			0x1
1196 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT		1
1197 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK			0x1
1198 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT		2
1199 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK			0x1
1200 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT			3
1201 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK			0x1
1202 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT			4
1203 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK			0x1
1204 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT			5
1205 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK			0x7
1206 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT			6
1207 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK			0x3
1208 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT			9
1209 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK			0x1
1210 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT			11
1211 #define RDIF_TASK_CONTEXT_RESERVED0_MASK			0x1
1212 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT			12
1213 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK		0x1
1214 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT		13
1215 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK	0x1
1216 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT	14
1217 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK	0x1
1218 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT	15
1219 	__le16 state;
1220 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK		0xF
1221 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT		0
1222 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK	0xF
1223 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT	4
1224 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK			0x1
1225 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT			8
1226 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK		0x1
1227 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT		9
1228 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK			0xF
1229 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT			10
1230 #define RDIF_TASK_CONTEXT_RESERVED1_MASK			0x3
1231 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT			14
1232 	__le32 reserved2;
1233 };
1234 
1235 /* Status block structure */
1236 struct status_block_e4 {
1237 	__le16	pi_array[PIS_PER_SB_E4];
1238 	__le32	sb_num;
1239 #define STATUS_BLOCK_E4_SB_NUM_MASK	0x1FF
1240 #define STATUS_BLOCK_E4_SB_NUM_SHIFT	0
1241 #define STATUS_BLOCK_E4_ZERO_PAD_MASK	0x7F
1242 #define STATUS_BLOCK_E4_ZERO_PAD_SHIFT	9
1243 #define STATUS_BLOCK_E4_ZERO_PAD2_MASK	0xFFFF
1244 #define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT	16
1245 	__le32 prod_index;
1246 #define STATUS_BLOCK_E4_PROD_INDEX_MASK		0xFFFFFF
1247 #define STATUS_BLOCK_E4_PROD_INDEX_SHIFT	0
1248 #define STATUS_BLOCK_E4_ZERO_PAD3_MASK		0xFF
1249 #define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT		24
1250 };
1251 
1252 /* Tdif context */
1253 struct tdif_task_context {
1254 	__le32 initial_ref_tag;
1255 	__le16 app_tag_value;
1256 	__le16 app_tag_mask;
1257 	__le16 partial_crc_value_b;
1258 	__le16 partial_checksum_value_b;
1259 	__le16 stateB;
1260 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK	0xF
1261 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT	0
1262 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK	0xF
1263 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT	4
1264 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK			0x1
1265 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT			8
1266 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK			0x1
1267 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT		9
1268 #define TDIF_TASK_CONTEXT_RESERVED0_MASK			0x3F
1269 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT			10
1270 	u8 reserved1;
1271 	u8 flags0;
1272 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK			0x1
1273 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT			0
1274 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK		0x1
1275 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT		1
1276 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK			0x1
1277 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT			2
1278 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK		0x1
1279 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT		3
1280 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK			0x3
1281 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT			4
1282 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK				0x1
1283 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT			6
1284 #define TDIF_TASK_CONTEXT_RESERVED2_MASK			0x1
1285 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT			7
1286 	__le32 flags1;
1287 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK			0x1
1288 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT			0
1289 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK			0x1
1290 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT		1
1291 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK			0x1
1292 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT		2
1293 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK			0x1
1294 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT			3
1295 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK			0x1
1296 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT			4
1297 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK			0x1
1298 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT			5
1299 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK			0x7
1300 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT			6
1301 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK			0x3
1302 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT			9
1303 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK			0x1
1304 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT			11
1305 #define TDIF_TASK_CONTEXT_RESERVED3_MASK			0x1
1306 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT			12
1307 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK		0x1
1308 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT		13
1309 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK	0xF
1310 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT	14
1311 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK	0xF
1312 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT	18
1313 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK			0x1
1314 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT			22
1315 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK		0x1
1316 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT		23
1317 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK			0xF
1318 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT			24
1319 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK	0x1
1320 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT	28
1321 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK	0x1
1322 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT	29
1323 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK		0x1
1324 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT		30
1325 #define TDIF_TASK_CONTEXT_RESERVED4_MASK			0x1
1326 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT			31
1327 	__le32 offset_in_io_b;
1328 	__le16 partial_crc_value_a;
1329 	__le16 partial_checksum_value_a;
1330 	__le32 offset_in_io_a;
1331 	u8 partial_dif_data_a[8];
1332 	u8 partial_dif_data_b[8];
1333 };
1334 
1335 /* Timers context */
1336 struct timers_context {
1337 	__le32 logical_client_0;
1338 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK	0x7FFFFFF
1339 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT	0
1340 #define TIMERS_CONTEXT_RESERVED0_MASK		0x1
1341 #define TIMERS_CONTEXT_RESERVED0_SHIFT		27
1342 #define TIMERS_CONTEXT_VALIDLC0_MASK		0x1
1343 #define TIMERS_CONTEXT_VALIDLC0_SHIFT		28
1344 #define TIMERS_CONTEXT_ACTIVELC0_MASK		0x1
1345 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT		29
1346 #define TIMERS_CONTEXT_RESERVED1_MASK		0x3
1347 #define TIMERS_CONTEXT_RESERVED1_SHIFT		30
1348 	__le32 logical_client_1;
1349 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK	0x7FFFFFF
1350 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT	0
1351 #define TIMERS_CONTEXT_RESERVED2_MASK		0x1
1352 #define TIMERS_CONTEXT_RESERVED2_SHIFT		27
1353 #define TIMERS_CONTEXT_VALIDLC1_MASK		0x1
1354 #define TIMERS_CONTEXT_VALIDLC1_SHIFT		28
1355 #define TIMERS_CONTEXT_ACTIVELC1_MASK		0x1
1356 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT		29
1357 #define TIMERS_CONTEXT_RESERVED3_MASK		0x3
1358 #define TIMERS_CONTEXT_RESERVED3_SHIFT		30
1359 	__le32 logical_client_2;
1360 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK	0x7FFFFFF
1361 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT	0
1362 #define TIMERS_CONTEXT_RESERVED4_MASK		0x1
1363 #define TIMERS_CONTEXT_RESERVED4_SHIFT		27
1364 #define TIMERS_CONTEXT_VALIDLC2_MASK		0x1
1365 #define TIMERS_CONTEXT_VALIDLC2_SHIFT		28
1366 #define TIMERS_CONTEXT_ACTIVELC2_MASK		0x1
1367 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT		29
1368 #define TIMERS_CONTEXT_RESERVED5_MASK		0x3
1369 #define TIMERS_CONTEXT_RESERVED5_SHIFT		30
1370 	__le32 host_expiration_fields;
1371 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK	0x7FFFFFF
1372 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT	0
1373 #define TIMERS_CONTEXT_RESERVED6_MASK			0x1
1374 #define TIMERS_CONTEXT_RESERVED6_SHIFT			27
1375 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK	0x1
1376 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT	 28
1377 #define TIMERS_CONTEXT_RESERVED7_MASK			0x7
1378 #define TIMERS_CONTEXT_RESERVED7_SHIFT			29
1379 };
1380 
1381 /* Enum for next_protocol field of tunnel_parsing_flags / tunnelTypeDesc */
1382 enum tunnel_next_protocol {
1383 	e_unknown = 0,
1384 	e_l2 = 1,
1385 	e_ipv4 = 2,
1386 	e_ipv6 = 3,
1387 	MAX_TUNNEL_NEXT_PROTOCOL
1388 };
1389 
1390 #endif /* __COMMON_HSI__ */
1391 #endif
1392