1 /*
2  * INET		An implementation of the TCP/IP protocol suite for the LINUX
3  *		operating system.  INET is implemented using the  BSD Socket
4  *		interface as the means of communication with the user level.
5  *
6  *		Global definitions for the Frame relay interface.
7  *
8  * Version:	@(#)if_ifrad.h	0.20	13 Apr 96
9  *
10  * Author:	Mike McLagan <mike.mclagan@linux.org>
11  *
12  * Changes:
13  *		0.15	Mike McLagan	Structure packing
14  *
15  *		0.20	Mike McLagan	New flags for S508 buffer handling
16  *
17  *		This program is free software; you can redistribute it and/or
18  *		modify it under the terms of the GNU General Public License
19  *		as published by the Free Software Foundation; either version
20  *		2 of the License, or (at your option) any later version.
21  */
22 #ifndef SDLA_H
23 #define SDLA_H
24 
25 #include <uapi/linux/sdla.h>
26 
27 
28 /* important Z80 window addresses */
29 #define SDLA_CONTROL_WND		0xE000
30 
31 #define SDLA_502_CMD_BUF		0xEF60
32 #define SDLA_502_RCV_BUF		0xA900
33 #define	SDLA_502_TXN_AVAIL		0xFFF1
34 #define SDLA_502_RCV_AVAIL		0xFFF2
35 #define SDLA_502_EVENT_FLAGS		0xFFF3
36 #define SDLA_502_MDM_STATUS		0xFFF4
37 #define SDLA_502_IRQ_INTERFACE		0xFFFD
38 #define SDLA_502_IRQ_PERMISSION		0xFFFE
39 #define SDLA_502_DATA_OFS		0x0010
40 
41 #define SDLA_508_CMD_BUF		0xE000
42 #define SDLA_508_TXBUF_INFO		0xF100
43 #define SDLA_508_RXBUF_INFO		0xF120
44 #define SDLA_508_EVENT_FLAGS		0xF003
45 #define SDLA_508_MDM_STATUS		0xF004
46 #define SDLA_508_IRQ_INTERFACE		0xF010
47 #define SDLA_508_IRQ_PERMISSION		0xF011
48 #define SDLA_508_TSE_OFFSET		0xF012
49 
50 /* Event flags */
51 #define SDLA_EVENT_STATUS		0x01
52 #define SDLA_EVENT_DLCI_STATUS		0x02
53 #define SDLA_EVENT_BAD_DLCI		0x04
54 #define SDLA_EVENT_LINK_DOWN		0x40
55 
56 /* IRQ Trigger flags */
57 #define SDLA_INTR_RX			0x01
58 #define SDLA_INTR_TX			0x02
59 #define SDLA_INTR_MODEM			0x04
60 #define SDLA_INTR_COMPLETE		0x08
61 #define SDLA_INTR_STATUS		0x10
62 #define SDLA_INTR_TIMER			0x20
63 
64 /* DLCI status bits */
65 #define SDLA_DLCI_DELETED		0x01
66 #define SDLA_DLCI_ACTIVE		0x02
67 #define SDLA_DLCI_WAITING		0x04
68 #define SDLA_DLCI_NEW			0x08
69 #define SDLA_DLCI_INCLUDED		0x40
70 
71 /* valid command codes */
72 #define	SDLA_INFORMATION_WRITE		0x01
73 #define	SDLA_INFORMATION_READ		0x02
74 #define SDLA_ISSUE_IN_CHANNEL_SIGNAL	0x03
75 #define	SDLA_SET_DLCI_CONFIGURATION	0x10
76 #define	SDLA_READ_DLCI_CONFIGURATION	0x11
77 #define	SDLA_DISABLE_COMMUNICATIONS	0x12
78 #define	SDLA_ENABLE_COMMUNICATIONS	0x13
79 #define	SDLA_READ_DLC_STATUS		0x14
80 #define	SDLA_READ_DLC_STATISTICS	0x15
81 #define	SDLA_FLUSH_DLC_STATISTICS	0x16
82 #define	SDLA_LIST_ACTIVE_DLCI		0x17
83 #define	SDLA_FLUSH_INFORMATION_BUFFERS	0x18
84 #define	SDLA_ADD_DLCI			0x20
85 #define	SDLA_DELETE_DLCI		0x21
86 #define	SDLA_ACTIVATE_DLCI		0x22
87 #define	SDLA_DEACTIVATE_DLCI		0x23
88 #define	SDLA_READ_MODEM_STATUS		0x30
89 #define	SDLA_SET_MODEM_STATUS		0x31
90 #define	SDLA_READ_COMMS_ERR_STATS	0x32
91 #define SDLA_FLUSH_COMMS_ERR_STATS	0x33
92 #define	SDLA_READ_CODE_VERSION		0x40
93 #define SDLA_SET_IRQ_TRIGGER		0x50
94 #define SDLA_GET_IRQ_TRIGGER		0x51
95 
96 /* In channel signal types */
97 #define SDLA_ICS_LINK_VERIFY		0x02
98 #define SDLA_ICS_STATUS_ENQ		0x03
99 
100 /* modem status flags */
101 #define SDLA_MODEM_DTR_HIGH		0x01
102 #define SDLA_MODEM_RTS_HIGH		0x02
103 #define SDLA_MODEM_DCD_HIGH		0x08
104 #define SDLA_MODEM_CTS_HIGH		0x20
105 
106 /* used for RET_MODEM interpretation */
107 #define SDLA_MODEM_DCD_LOW		0x01
108 #define SDLA_MODEM_CTS_LOW		0x02
109 
110 /* return codes */
111 #define SDLA_RET_OK			0x00
112 #define SDLA_RET_COMMUNICATIONS		0x01
113 #define SDLA_RET_CHANNEL_INACTIVE	0x02
114 #define SDLA_RET_DLCI_INACTIVE		0x03
115 #define SDLA_RET_DLCI_CONFIG		0x04
116 #define SDLA_RET_BUF_TOO_BIG		0x05
117 #define SDLA_RET_NO_DATA		0x05
118 #define SDLA_RET_BUF_OVERSIZE		0x06
119 #define SDLA_RET_CIR_OVERFLOW		0x07
120 #define SDLA_RET_NO_BUFS		0x08
121 #define SDLA_RET_TIMEOUT		0x0A
122 #define SDLA_RET_MODEM			0x10
123 #define SDLA_RET_CHANNEL_OFF		0x11
124 #define SDLA_RET_CHANNEL_ON		0x12
125 #define SDLA_RET_DLCI_STATUS		0x13
126 #define SDLA_RET_DLCI_UNKNOWN       	0x14
127 #define SDLA_RET_COMMAND_INVALID    	0x1F
128 
129 /* Configuration flags */
130 #define SDLA_DIRECT_RECV		0x0080
131 #define SDLA_TX_NO_EXCEPT		0x0020
132 #define SDLA_NO_ICF_MSGS		0x1000
133 #define SDLA_TX50_RX50			0x0000
134 #define SDLA_TX70_RX30			0x2000
135 #define SDLA_TX30_RX70			0x4000
136 
137 /* IRQ selection flags */
138 #define SDLA_IRQ_RECEIVE		0x01
139 #define SDLA_IRQ_TRANSMIT		0x02
140 #define SDLA_IRQ_MODEM_STAT		0x04
141 #define SDLA_IRQ_COMMAND		0x08
142 #define SDLA_IRQ_CHANNEL		0x10
143 #define SDLA_IRQ_TIMER			0x20
144 
145 /* definitions for PC memory mapping */
146 #define SDLA_8K_WINDOW			0x01
147 #define SDLA_S502_SEG_A			0x10
148 #define SDLA_S502_SEG_C			0x20
149 #define SDLA_S502_SEG_D			0x00
150 #define SDLA_S502_SEG_E			0x30
151 #define SDLA_S507_SEG_A			0x00
152 #define SDLA_S507_SEG_B			0x40
153 #define SDLA_S507_SEG_C			0x80
154 #define SDLA_S507_SEG_E			0xC0
155 #define SDLA_S508_SEG_A			0x00
156 #define SDLA_S508_SEG_C			0x10
157 #define SDLA_S508_SEG_D			0x08
158 #define SDLA_S508_SEG_E			0x18
159 
160 /* SDLA adapter port constants */
161 #define SDLA_IO_EXTENTS			0x04
162 
163 #define SDLA_REG_CONTROL		0x00
164 #define SDLA_REG_PC_WINDOW		0x01	/* offset for PC window select latch */
165 #define SDLA_REG_Z80_WINDOW 		0x02	/* offset for Z80 window select latch */
166 #define SDLA_REG_Z80_CONTROL		0x03	/* offset for Z80 control latch */
167 
168 #define SDLA_S502_STS			0x00	/* status reg for 502, 502E, 507 */
169 #define SDLA_S508_GNRL			0x00	/* general purp. reg for 508 */
170 #define SDLA_S508_STS			0x01	/* status reg for 508 */
171 #define SDLA_S508_IDR			0x02	/* ID reg for 508 */
172 
173 /* control register flags */
174 #define SDLA_S502A_START		0x00	/* start the CPU */
175 #define SDLA_S502A_INTREQ		0x02
176 #define SDLA_S502A_INTEN		0x04
177 #define SDLA_S502A_HALT			0x08	/* halt the CPU */
178 #define SDLA_S502A_NMI			0x10	/* issue an NMI to the CPU */
179 
180 #define SDLA_S502E_CPUEN		0x01
181 #define SDLA_S502E_ENABLE		0x02
182 #define SDLA_S502E_INTACK		0x04
183 
184 #define SDLA_S507_ENABLE		0x01
185 #define SDLA_S507_IRQ3			0x00
186 #define SDLA_S507_IRQ4			0x20
187 #define SDLA_S507_IRQ5			0x40
188 #define SDLA_S507_IRQ7			0x60
189 #define SDLA_S507_IRQ10			0x80
190 #define SDLA_S507_IRQ11			0xA0
191 #define SDLA_S507_IRQ12			0xC0
192 #define SDLA_S507_IRQ15			0xE0
193 
194 #define SDLA_HALT			0x00
195 #define SDLA_CPUEN			0x02
196 #define SDLA_MEMEN			0x04
197 #define SDLA_S507_EPROMWR		0x08
198 #define SDLA_S507_EPROMCLK		0x10
199 #define SDLA_S508_INTRQ			0x08
200 #define SDLA_S508_INTEN			0x10
201 
202 struct sdla_cmd {
203    char  opp_flag;
204    char  cmd;
205    short length;
206    char  retval;
207    short dlci;
208    char  flags;
209    short rxlost_int;
210    long  rxlost_app;
211    char  reserve[2];
212    char  data[SDLA_MAX_DATA];	/* transfer data buffer */
213 } __attribute__((packed));
214 
215 struct intr_info {
216    char  flags;
217    short txlen;
218    char  irq;
219    char  flags2;
220    short timeout;
221 } __attribute__((packed));
222 
223 /* found in the 508's control window at RXBUF_INFO */
224 struct buf_info {
225    unsigned short rse_num;
226    unsigned long  rse_base;
227    unsigned long  rse_next;
228    unsigned long  buf_base;
229    unsigned short reserved;
230    unsigned long  buf_top;
231 } __attribute__((packed));
232 
233 /* structure pointed to by rse_base in RXBUF_INFO struct */
234 struct buf_entry {
235    char  opp_flag;
236    short length;
237    short dlci;
238    char  flags;
239    short timestamp;
240    short reserved[2];
241    long  buf_addr;
242 } __attribute__((packed));
243 
244 #endif
245