1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2012-2016 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Previously licensed under the ISC license by Qualcomm Atheros, Inc. 5*5113495bSYour Name * 6*5113495bSYour Name * 7*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 8*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 9*5113495bSYour Name * above copyright notice and this permission notice appear in all 10*5113495bSYour Name * copies. 11*5113495bSYour Name * 12*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 13*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 14*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 15*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 16*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 17*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 18*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 19*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 20*5113495bSYour Name */ 21*5113495bSYour Name 22*5113495bSYour Name /* 23*5113495bSYour Name * This file was originally distributed by Qualcomm Atheros, Inc. 24*5113495bSYour Name * under proprietary terms before Copyright ownership was assigned 25*5113495bSYour Name * to the Linux Foundation. 26*5113495bSYour Name */ 27*5113495bSYour Name 28*5113495bSYour Name #ifndef __CEPCI_H__ 29*5113495bSYour Name #define __CEPCI_H__ 30*5113495bSYour Name 31*5113495bSYour Name /* 32*5113495bSYour Name * Support for Copy Engine over PCI. 33*5113495bSYour Name * Structures shared between Host software and Target firmware. 34*5113495bSYour Name */ 35*5113495bSYour Name #include <a_types.h> /* A_UINT32 */ 36*5113495bSYour Name 37*5113495bSYour Name /* 38*5113495bSYour Name * Total number of PCIe MSI interrupts requested for all interrupt sources. 39*5113495bSYour Name * PCIe standard forces this to be a power of 2. 40*5113495bSYour Name * Some Host OS's limit MSI requests that can be granted to 8 41*5113495bSYour Name * so for now we abide by this limit and avoid requesting more 42*5113495bSYour Name * than that. 43*5113495bSYour Name */ 44*5113495bSYour Name #define MSI_NUM_REQUEST_LOG2 3 45*5113495bSYour Name #define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2) 46*5113495bSYour Name 47*5113495bSYour Name /* 48*5113495bSYour Name * Granted MSIs are assigned as follows: 49*5113495bSYour Name * Firmware uses the first 50*5113495bSYour Name * Remaining MSIs, if any, are used by Copy Engines 51*5113495bSYour Name * This mapping is known to both Target firmware and Host software. 52*5113495bSYour Name * It may be changed as long as Host and Target are kept in sync. 53*5113495bSYour Name */ 54*5113495bSYour Name #define MSI_ASSIGN_FW 0 /* 1 MSI for firmware (errors, etc.) */ 55*5113495bSYour Name #define MSI_ASSIGN_CE_INITIAL 1 /* 7 MSIs for Copy Engines */ 56*5113495bSYour Name #define MSI_ASSIGN_CE_MAX 7 57*5113495bSYour Name 58*5113495bSYour Name 59*5113495bSYour Name 60*5113495bSYour Name 61*5113495bSYour Name /* 62*5113495bSYour Name * PCI-specific Target state. Much of this may be of interest 63*5113495bSYour Name * to the Host so HOST_INTEREST->hi_interconnect_state points 64*5113495bSYour Name * here (and all members are 32-bit quantities in order to 65*5113495bSYour Name * facilitate Host access). In particular, Host software is 66*5113495bSYour Name * required to initialize pipe_cfg_addr and svc_to_pipe_map. 67*5113495bSYour Name */ 68*5113495bSYour Name struct pcie_state_s { 69*5113495bSYour Name A_UINT32 pipe_cfg_addr; /* Pipe configuration Target address */ 70*5113495bSYour Name /* NB: CE_pipe_config[CE_COUNT] */ 71*5113495bSYour Name 72*5113495bSYour Name A_UINT32 svc_to_pipe_map; /* Service to pipe map Target address */ 73*5113495bSYour Name /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */ 74*5113495bSYour Name 75*5113495bSYour Name A_UINT32 MSI_requested; /* number of MSI interrupts requested */ 76*5113495bSYour Name A_UINT32 MSI_granted; /* number of MSI interrupts granted */ 77*5113495bSYour Name A_UINT32 MSI_addr; /* Message Signalled Interrupt address */ 78*5113495bSYour Name A_UINT32 MSI_data; /* Base data */ 79*5113495bSYour Name A_UINT32 MSI_fw_intr_data; /* Data for firmware interrupt; 80*5113495bSYour Name MSI data for other interrupts are 81*5113495bSYour Name in various SoC registers */ 82*5113495bSYour Name 83*5113495bSYour Name A_UINT32 power_mgmt_method; /* PCIE_PWR_METHOD_* */ 84*5113495bSYour Name A_UINT32 config_flags; /* PCIE_CONFIG_FLAG_* */ 85*5113495bSYour Name }; 86*5113495bSYour Name 87*5113495bSYour Name /* 88*5113495bSYour Name * PCIE_CONFIG_FLAG definitions 89*5113495bSYour Name */ 90*5113495bSYour Name 91*5113495bSYour Name #define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001 92*5113495bSYour Name #define CE_PKTLOG_PIPE 8 /* used by both host and target side */ 93*5113495bSYour Name 94*5113495bSYour Name #define PCIE_CONFIG_FLAG_CLK_GATING_L1 0x0000001 95*5113495bSYour Name #define PCIE_CONFIG_FLAG_CLK_SWITCH_WAIT 0x0000002 96*5113495bSYour Name #define PCIE_CONFIG_FLAG_AXI_CLK_GATE 0x0000004 97*5113495bSYour Name #define PCIE_CONFIG_FLAG_CLK_REQ_L1 0x0000008 98*5113495bSYour Name 99*5113495bSYour Name #define PIPE_TO_CE_MAP_CNT 32 /* simple implementation constant */ 100*5113495bSYour Name 101*5113495bSYour Name /* 102*5113495bSYour Name * Configuration information for a Copy Engine pipe. 103*5113495bSYour Name * Passed from Host to Target during startup (one per CE). 104*5113495bSYour Name */ 105*5113495bSYour Name struct CE_pipe_config { 106*5113495bSYour Name A_UINT32 pipenum; 107*5113495bSYour Name A_UINT32 pipedir; 108*5113495bSYour Name A_UINT32 nentries; 109*5113495bSYour Name A_UINT32 nbytes_max; 110*5113495bSYour Name A_UINT32 flags; 111*5113495bSYour Name A_UINT32 reserved; 112*5113495bSYour Name }; 113*5113495bSYour Name 114*5113495bSYour Name #endif /* __CEPCI_H__ */ 115