xref: /wlan-driver/fw-api/hw/kiwi/v1/msmhwiobase.h (revision 5113495b16420b49004c444715d2daae2066e7dc) 
1*5113495bSYour Name 
2*5113495bSYour Name /*
3*5113495bSYour Name  * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
4*5113495bSYour Name  *
5*5113495bSYour Name  * Permission to use, copy, modify, and/or distribute this software for
6*5113495bSYour Name  * any purpose with or without fee is hereby granted, provided that the
7*5113495bSYour Name  * above copyright notice and this permission notice appear in all
8*5113495bSYour Name  * copies.
9*5113495bSYour Name  *
10*5113495bSYour Name  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11*5113495bSYour Name  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12*5113495bSYour Name  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13*5113495bSYour Name  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14*5113495bSYour Name  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15*5113495bSYour Name  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16*5113495bSYour Name  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17*5113495bSYour Name  * PERFORMANCE OF THIS SOFTWARE.
18*5113495bSYour Name  */
19*5113495bSYour Name 
20*5113495bSYour Name 
21*5113495bSYour Name 
22*5113495bSYour Name 
23*5113495bSYour Name #ifndef __MSMHWIOBASE_H__
24*5113495bSYour Name #define __MSMHWIOBASE_H__
25*5113495bSYour Name 
26*5113495bSYour Name 
27*5113495bSYour Name 
28*5113495bSYour Name 
29*5113495bSYour Name 
30*5113495bSYour Name #define WCSS_WCSS_BASE                                              0x00000000
31*5113495bSYour Name #define WCSS_WCSS_BASE_SIZE                                         0x01000000
32*5113495bSYour Name #define WCSS_WCSS_BASE_PHYS                                         0x00000000
33*5113495bSYour Name 
34*5113495bSYour Name 
35*5113495bSYour Name 
36*5113495bSYour Name #define QDSS_STM_SIZE_BASE                                          0x00100000
37*5113495bSYour Name #define QDSS_STM_SIZE_BASE_SIZE                                     0x100000000
38*5113495bSYour Name #define QDSS_STM_SIZE_BASE_PHYS                                     0x00100000
39*5113495bSYour Name 
40*5113495bSYour Name 
41*5113495bSYour Name 
42*5113495bSYour Name #define BOOT_ROM_SIZE_BASE                                          0x00200000
43*5113495bSYour Name #define BOOT_ROM_SIZE_BASE_SIZE                                     0x100000000
44*5113495bSYour Name #define BOOT_ROM_SIZE_BASE_PHYS                                     0x00200000
45*5113495bSYour Name 
46*5113495bSYour Name 
47*5113495bSYour Name 
48*5113495bSYour Name #define SYSTEM_IRAM_SIZE_BASE                                       0x00400000
49*5113495bSYour Name #define SYSTEM_IRAM_SIZE_BASE_SIZE                                  0x100000000
50*5113495bSYour Name #define SYSTEM_IRAM_SIZE_BASE_PHYS                                  0x00400000
51*5113495bSYour Name 
52*5113495bSYour Name 
53*5113495bSYour Name 
54*5113495bSYour Name #define BOOT_ROM_START_ADDRESS_BASE                                 0x01200000
55*5113495bSYour Name #define BOOT_ROM_START_ADDRESS_BASE_SIZE                            0x100000000
56*5113495bSYour Name #define BOOT_ROM_START_ADDRESS_BASE_PHYS                            0x01200000
57*5113495bSYour Name 
58*5113495bSYour Name 
59*5113495bSYour Name 
60*5113495bSYour Name #define BOOT_ROM_END_ADDRESS_BASE                                   0x013fffff
61*5113495bSYour Name #define BOOT_ROM_END_ADDRESS_BASE_SIZE                              0x100000000
62*5113495bSYour Name #define BOOT_ROM_END_ADDRESS_BASE_PHYS                              0x013fffff
63*5113495bSYour Name 
64*5113495bSYour Name 
65*5113495bSYour Name 
66*5113495bSYour Name #define SYSTEM_IRAM_START_ADDRESS_BASE                              0x01400000
67*5113495bSYour Name #define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE                         0x100000000
68*5113495bSYour Name #define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS                         0x01400000
69*5113495bSYour Name 
70*5113495bSYour Name 
71*5113495bSYour Name 
72*5113495bSYour Name #define SYSTEM_IRAM_END_ADDRESS_BASE                                0x017fffff
73*5113495bSYour Name #define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE                           0x100000000
74*5113495bSYour Name #define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS                           0x017fffff
75*5113495bSYour Name 
76*5113495bSYour Name 
77*5113495bSYour Name 
78*5113495bSYour Name #define QDSS_STM_BASE                                               0x01800000
79*5113495bSYour Name #define QDSS_STM_BASE_SIZE                                          0x100000000
80*5113495bSYour Name #define QDSS_STM_BASE_PHYS                                          0x01800000
81*5113495bSYour Name 
82*5113495bSYour Name 
83*5113495bSYour Name 
84*5113495bSYour Name #define QDSS_STM_END_BASE                                           0x018fffff
85*5113495bSYour Name #define QDSS_STM_END_BASE_SIZE                                      0x100000000
86*5113495bSYour Name #define QDSS_STM_END_BASE_PHYS                                      0x018fffff
87*5113495bSYour Name 
88*5113495bSYour Name 
89*5113495bSYour Name 
90*5113495bSYour Name #define TLMM_BASE                                                   0x01900000
91*5113495bSYour Name #define TLMM_BASE_SIZE                                              0x00200000
92*5113495bSYour Name #define TLMM_BASE_PHYS                                              0x01900000
93*5113495bSYour Name 
94*5113495bSYour Name 
95*5113495bSYour Name 
96*5113495bSYour Name #define CORE_TOP_CSR_BASE                                           0x01b00000
97*5113495bSYour Name #define CORE_TOP_CSR_BASE_SIZE                                      0x00040000
98*5113495bSYour Name #define CORE_TOP_CSR_BASE_PHYS                                      0x01b00000
99*5113495bSYour Name 
100*5113495bSYour Name 
101*5113495bSYour Name 
102*5113495bSYour Name #define BLSP1_BLSP_BASE                                             0x01b40000
103*5113495bSYour Name #define BLSP1_BLSP_BASE_SIZE                                        0x00040000
104*5113495bSYour Name #define BLSP1_BLSP_BASE_PHYS                                        0x01b40000
105*5113495bSYour Name 
106*5113495bSYour Name 
107*5113495bSYour Name 
108*5113495bSYour Name #define SOC_WFSS_CE_REG_BASE                                        0x01b80000
109*5113495bSYour Name #define SOC_WFSS_CE_REG_BASE_SIZE                                   0x0001c000
110*5113495bSYour Name #define SOC_WFSS_CE_REG_BASE_PHYS                                   0x01b80000
111*5113495bSYour Name 
112*5113495bSYour Name 
113*5113495bSYour Name 
114*5113495bSYour Name #define WL_TLMM_BASE                                                0x01bc0000
115*5113495bSYour Name #define WL_TLMM_BASE_SIZE                                           0x00020000
116*5113495bSYour Name #define WL_TLMM_BASE_PHYS                                           0x01bc0000
117*5113495bSYour Name 
118*5113495bSYour Name 
119*5113495bSYour Name 
120*5113495bSYour Name #define MEMSS_CSR_BASE                                              0x01be0000
121*5113495bSYour Name #define MEMSS_CSR_BASE_SIZE                                         0x0000001c
122*5113495bSYour Name #define MEMSS_CSR_BASE_PHYS                                         0x01be0000
123*5113495bSYour Name 
124*5113495bSYour Name 
125*5113495bSYour Name 
126*5113495bSYour Name #define TSENS_SROT_BASE                                             0x01bf0000
127*5113495bSYour Name #define TSENS_SROT_BASE_SIZE                                        0x00001000
128*5113495bSYour Name #define TSENS_SROT_BASE_PHYS                                        0x01bf0000
129*5113495bSYour Name 
130*5113495bSYour Name 
131*5113495bSYour Name 
132*5113495bSYour Name #define TSENS_TM_BASE                                               0x01bf1000
133*5113495bSYour Name #define TSENS_TM_BASE_SIZE                                          0x00001000
134*5113495bSYour Name #define TSENS_TM_BASE_PHYS                                          0x01bf1000
135*5113495bSYour Name 
136*5113495bSYour Name 
137*5113495bSYour Name 
138*5113495bSYour Name #define QDSS_APB_DEC_QDSS_APB_BASE                                  0x01c00000
139*5113495bSYour Name #define QDSS_APB_DEC_QDSS_APB_BASE_SIZE                             0x00080000
140*5113495bSYour Name #define QDSS_APB_DEC_QDSS_APB_BASE_PHYS                             0x01c00000
141*5113495bSYour Name 
142*5113495bSYour Name 
143*5113495bSYour Name 
144*5113495bSYour Name #define QDSS_WRAPPER_TOP_BASE                                       0x01c80000
145*5113495bSYour Name #define QDSS_WRAPPER_TOP_BASE_SIZE                                  0x0007fffd
146*5113495bSYour Name #define QDSS_WRAPPER_TOP_BASE_PHYS                                  0x01c80000
147*5113495bSYour Name 
148*5113495bSYour Name 
149*5113495bSYour Name 
150*5113495bSYour Name #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE                 0x01d00000
151*5113495bSYour Name #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE            0x00100000
152*5113495bSYour Name #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS            0x01d00000
153*5113495bSYour Name 
154*5113495bSYour Name 
155*5113495bSYour Name 
156*5113495bSYour Name #define PCIE_PCIE_TOP_WRAPPER_BASE                                  0x01e00000
157*5113495bSYour Name #define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE                             0x00020000
158*5113495bSYour Name #define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS                             0x01e00000
159*5113495bSYour Name 
160*5113495bSYour Name 
161*5113495bSYour Name 
162*5113495bSYour Name #define SECURITY_CONTROL_WLAN_BASE                                  0x01e20000
163*5113495bSYour Name #define SECURITY_CONTROL_WLAN_BASE_SIZE                             0x00008000
164*5113495bSYour Name #define SECURITY_CONTROL_WLAN_BASE_PHYS                             0x01e20000
165*5113495bSYour Name 
166*5113495bSYour Name 
167*5113495bSYour Name 
168*5113495bSYour Name #define EDPD_CAL_ACC_BASE                                           0x01e28000
169*5113495bSYour Name #define EDPD_CAL_ACC_BASE_SIZE                                      0x00003000
170*5113495bSYour Name #define EDPD_CAL_ACC_BASE_PHYS                                      0x01e28000
171*5113495bSYour Name 
172*5113495bSYour Name 
173*5113495bSYour Name 
174*5113495bSYour Name #define CPR_CX_CPR3_BASE                                            0x01e30000
175*5113495bSYour Name #define CPR_CX_CPR3_BASE_SIZE                                       0x00004000
176*5113495bSYour Name #define CPR_CX_CPR3_BASE_PHYS                                       0x01e30000
177*5113495bSYour Name 
178*5113495bSYour Name 
179*5113495bSYour Name 
180*5113495bSYour Name #define CPR_MX_CPR3_BASE                                            0x01e34000
181*5113495bSYour Name #define CPR_MX_CPR3_BASE_SIZE                                       0x00004000
182*5113495bSYour Name #define CPR_MX_CPR3_BASE_PHYS                                       0x01e34000
183*5113495bSYour Name 
184*5113495bSYour Name 
185*5113495bSYour Name 
186*5113495bSYour Name #define GCC_GCC_BASE                                                0x01e40000
187*5113495bSYour Name #define GCC_GCC_BASE_SIZE                                           0x000003e8
188*5113495bSYour Name #define GCC_GCC_BASE_PHYS                                           0x01e40000
189*5113495bSYour Name 
190*5113495bSYour Name 
191*5113495bSYour Name 
192*5113495bSYour Name #define PRNG_PRNG_TOP_BASE                                          0x01e50000
193*5113495bSYour Name #define PRNG_PRNG_TOP_BASE_SIZE                                     0x00010000
194*5113495bSYour Name #define PRNG_PRNG_TOP_BASE_PHYS                                     0x01e50000
195*5113495bSYour Name 
196*5113495bSYour Name 
197*5113495bSYour Name 
198*5113495bSYour Name #define PCNOC_0_BUS_TIMEOUT_BASE                                    0x01e60000
199*5113495bSYour Name #define PCNOC_0_BUS_TIMEOUT_BASE_SIZE                               0x00001000
200*5113495bSYour Name #define PCNOC_0_BUS_TIMEOUT_BASE_PHYS                               0x01e60000
201*5113495bSYour Name 
202*5113495bSYour Name 
203*5113495bSYour Name 
204*5113495bSYour Name #define PCNOC_1_BUS_TIMEOUT_BASE                                    0x01e61000
205*5113495bSYour Name #define PCNOC_1_BUS_TIMEOUT_BASE_SIZE                               0x00001000
206*5113495bSYour Name #define PCNOC_1_BUS_TIMEOUT_BASE_PHYS                               0x01e61000
207*5113495bSYour Name 
208*5113495bSYour Name 
209*5113495bSYour Name 
210*5113495bSYour Name #define PCNOC_2_BUS_TIMEOUT_BASE                                    0x01e62000
211*5113495bSYour Name #define PCNOC_2_BUS_TIMEOUT_BASE_SIZE                               0x00001000
212*5113495bSYour Name #define PCNOC_2_BUS_TIMEOUT_BASE_PHYS                               0x01e62000
213*5113495bSYour Name 
214*5113495bSYour Name 
215*5113495bSYour Name 
216*5113495bSYour Name #define PCNOC_3_BUS_TIMEOUT_BASE                                    0x01e63000
217*5113495bSYour Name #define PCNOC_3_BUS_TIMEOUT_BASE_SIZE                               0x00001000
218*5113495bSYour Name #define PCNOC_3_BUS_TIMEOUT_BASE_PHYS                               0x01e63000
219*5113495bSYour Name 
220*5113495bSYour Name 
221*5113495bSYour Name 
222*5113495bSYour Name #define RRI_PREFETCH_REG_BASE                                       0x01e70000
223*5113495bSYour Name #define RRI_PREFETCH_REG_BASE_SIZE                                  0x00010000
224*5113495bSYour Name #define RRI_PREFETCH_REG_BASE_PHYS                                  0x01e70000
225*5113495bSYour Name 
226*5113495bSYour Name 
227*5113495bSYour Name 
228*5113495bSYour Name #define SYSTEM_NOC_BASE                                             0x01e80000
229*5113495bSYour Name #define SYSTEM_NOC_BASE_SIZE                                        0x0000a000
230*5113495bSYour Name #define SYSTEM_NOC_BASE_PHYS                                        0x01e80000
231*5113495bSYour Name 
232*5113495bSYour Name 
233*5113495bSYour Name 
234*5113495bSYour Name #define PC_NOC_BASE                                                 0x01f00000
235*5113495bSYour Name #define PC_NOC_BASE_SIZE                                            0x00003880
236*5113495bSYour Name #define PC_NOC_BASE_PHYS                                            0x01f00000
237*5113495bSYour Name 
238*5113495bSYour Name 
239*5113495bSYour Name 
240*5113495bSYour Name #define WLAON_WL_AON_REG_BASE                                       0x01f80000
241*5113495bSYour Name #define WLAON_WL_AON_REG_BASE_SIZE                                  0x000007c8
242*5113495bSYour Name #define WLAON_WL_AON_REG_BASE_PHYS                                  0x01f80000
243*5113495bSYour Name 
244*5113495bSYour Name 
245*5113495bSYour Name 
246*5113495bSYour Name #define SYSPM_SYSPM_REG_BASE                                        0x01f82000
247*5113495bSYour Name #define SYSPM_SYSPM_REG_BASE_SIZE                                   0x00001000
248*5113495bSYour Name #define SYSPM_SYSPM_REG_BASE_PHYS                                   0x01f82000
249*5113495bSYour Name 
250*5113495bSYour Name 
251*5113495bSYour Name 
252*5113495bSYour Name #define PMU_WLAN_PMU_TOP_BASE                                       0x01f88000
253*5113495bSYour Name #define PMU_WLAN_PMU_TOP_BASE_SIZE                                  0x00000340
254*5113495bSYour Name #define PMU_WLAN_PMU_TOP_BASE_PHYS                                  0x01f88000
255*5113495bSYour Name 
256*5113495bSYour Name 
257*5113495bSYour Name 
258*5113495bSYour Name #define PMU_NOC_BASE                                                0x01f8a000
259*5113495bSYour Name #define PMU_NOC_BASE_SIZE                                           0x00000080
260*5113495bSYour Name #define PMU_NOC_BASE_PHYS                                           0x01f8a000
261*5113495bSYour Name 
262*5113495bSYour Name 
263*5113495bSYour Name 
264*5113495bSYour Name #define PCIE_ATU_REGION_BASE                                        0x04000000
265*5113495bSYour Name #define PCIE_ATU_REGION_BASE_SIZE                                   0x100000000
266*5113495bSYour Name #define PCIE_ATU_REGION_BASE_PHYS                                   0x04000000
267*5113495bSYour Name 
268*5113495bSYour Name 
269*5113495bSYour Name 
270*5113495bSYour Name #define PCIE_ATU_REGION_SIZE_BASE                                   0x40000000
271*5113495bSYour Name #define PCIE_ATU_REGION_SIZE_BASE_SIZE                              0x100000000
272*5113495bSYour Name #define PCIE_ATU_REGION_SIZE_BASE_PHYS                              0x40000000
273*5113495bSYour Name 
274*5113495bSYour Name 
275*5113495bSYour Name 
276*5113495bSYour Name #define PCIE_ATU_REGION_END_BASE                                    0x43ffffff
277*5113495bSYour Name #define PCIE_ATU_REGION_END_BASE_SIZE                               0x100000000
278*5113495bSYour Name #define PCIE_ATU_REGION_END_BASE_PHYS                               0x43ffffff
279*5113495bSYour Name 
280*5113495bSYour Name 
281*5113495bSYour Name #endif
282