1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 #ifndef __MSMHWIOBASE_H__ 24 #define __MSMHWIOBASE_H__ 25 26 27 28 29 30 #define WCSS_WCSS_BASE 0x00000000 31 #define WCSS_WCSS_BASE_SIZE 0x01000000 32 #define WCSS_WCSS_BASE_PHYS 0x00000000 33 34 35 36 #define QDSS_STM_SIZE_BASE 0x00100000 37 #define QDSS_STM_SIZE_BASE_SIZE 0x100000000 38 #define QDSS_STM_SIZE_BASE_PHYS 0x00100000 39 40 41 42 #define BOOT_ROM_SIZE_BASE 0x00200000 43 #define BOOT_ROM_SIZE_BASE_SIZE 0x100000000 44 #define BOOT_ROM_SIZE_BASE_PHYS 0x00200000 45 46 47 48 #define SYSTEM_IRAM_SIZE_BASE 0x00400000 49 #define SYSTEM_IRAM_SIZE_BASE_SIZE 0x100000000 50 #define SYSTEM_IRAM_SIZE_BASE_PHYS 0x00400000 51 52 53 54 #define BOOT_ROM_START_ADDRESS_BASE 0x01200000 55 #define BOOT_ROM_START_ADDRESS_BASE_SIZE 0x100000000 56 #define BOOT_ROM_START_ADDRESS_BASE_PHYS 0x01200000 57 58 59 60 #define BOOT_ROM_END_ADDRESS_BASE 0x013fffff 61 #define BOOT_ROM_END_ADDRESS_BASE_SIZE 0x100000000 62 #define BOOT_ROM_END_ADDRESS_BASE_PHYS 0x013fffff 63 64 65 66 #define SYSTEM_IRAM_START_ADDRESS_BASE 0x01400000 67 #define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE 0x100000000 68 #define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS 0x01400000 69 70 71 72 #define SYSTEM_IRAM_END_ADDRESS_BASE 0x017fffff 73 #define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE 0x100000000 74 #define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS 0x017fffff 75 76 77 78 #define QDSS_STM_BASE 0x01800000 79 #define QDSS_STM_BASE_SIZE 0x100000000 80 #define QDSS_STM_BASE_PHYS 0x01800000 81 82 83 84 #define QDSS_STM_END_BASE 0x018fffff 85 #define QDSS_STM_END_BASE_SIZE 0x100000000 86 #define QDSS_STM_END_BASE_PHYS 0x018fffff 87 88 89 90 #define TLMM_BASE 0x01900000 91 #define TLMM_BASE_SIZE 0x00200000 92 #define TLMM_BASE_PHYS 0x01900000 93 94 95 96 #define CORE_TOP_CSR_BASE 0x01b00000 97 #define CORE_TOP_CSR_BASE_SIZE 0x00040000 98 #define CORE_TOP_CSR_BASE_PHYS 0x01b00000 99 100 101 102 #define BLSP1_BLSP_BASE 0x01b40000 103 #define BLSP1_BLSP_BASE_SIZE 0x00040000 104 #define BLSP1_BLSP_BASE_PHYS 0x01b40000 105 106 107 108 #define SOC_WFSS_CE_REG_BASE 0x01b80000 109 #define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000 110 #define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000 111 112 113 114 #define WL_TLMM_BASE 0x01bc0000 115 #define WL_TLMM_BASE_SIZE 0x00020000 116 #define WL_TLMM_BASE_PHYS 0x01bc0000 117 118 119 120 #define MEMSS_CSR_BASE 0x01be0000 121 #define MEMSS_CSR_BASE_SIZE 0x0000001c 122 #define MEMSS_CSR_BASE_PHYS 0x01be0000 123 124 125 126 #define TSENS_SROT_BASE 0x01bf0000 127 #define TSENS_SROT_BASE_SIZE 0x00001000 128 #define TSENS_SROT_BASE_PHYS 0x01bf0000 129 130 131 132 #define TSENS_TM_BASE 0x01bf1000 133 #define TSENS_TM_BASE_SIZE 0x00001000 134 #define TSENS_TM_BASE_PHYS 0x01bf1000 135 136 137 138 #define QDSS_APB_DEC_QDSS_APB_BASE 0x01c00000 139 #define QDSS_APB_DEC_QDSS_APB_BASE_SIZE 0x00080000 140 #define QDSS_APB_DEC_QDSS_APB_BASE_PHYS 0x01c00000 141 142 143 144 #define QDSS_WRAPPER_TOP_BASE 0x01c80000 145 #define QDSS_WRAPPER_TOP_BASE_SIZE 0x0007fffd 146 #define QDSS_WRAPPER_TOP_BASE_PHYS 0x01c80000 147 148 149 150 #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE 0x01d00000 151 #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE 0x00100000 152 #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS 0x01d00000 153 154 155 156 #define PCIE_PCIE_TOP_WRAPPER_BASE 0x01e00000 157 #define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000 158 #define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000 159 160 161 162 #define SECURITY_CONTROL_WLAN_BASE 0x01e20000 163 #define SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000 164 #define SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000 165 166 167 168 #define EDPD_CAL_ACC_BASE 0x01e28000 169 #define EDPD_CAL_ACC_BASE_SIZE 0x00003000 170 #define EDPD_CAL_ACC_BASE_PHYS 0x01e28000 171 172 173 174 #define CPR_CX_CPR3_BASE 0x01e30000 175 #define CPR_CX_CPR3_BASE_SIZE 0x00004000 176 #define CPR_CX_CPR3_BASE_PHYS 0x01e30000 177 178 179 180 #define CPR_MX_CPR3_BASE 0x01e34000 181 #define CPR_MX_CPR3_BASE_SIZE 0x00004000 182 #define CPR_MX_CPR3_BASE_PHYS 0x01e34000 183 184 185 186 #define GCC_GCC_BASE 0x01e40000 187 #define GCC_GCC_BASE_SIZE 0x000003e8 188 #define GCC_GCC_BASE_PHYS 0x01e40000 189 190 191 192 #define PRNG_PRNG_TOP_BASE 0x01e50000 193 #define PRNG_PRNG_TOP_BASE_SIZE 0x00010000 194 #define PRNG_PRNG_TOP_BASE_PHYS 0x01e50000 195 196 197 198 #define PCNOC_0_BUS_TIMEOUT_BASE 0x01e60000 199 #define PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000 200 #define PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000 201 202 203 204 #define PCNOC_1_BUS_TIMEOUT_BASE 0x01e61000 205 #define PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000 206 #define PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000 207 208 209 210 #define PCNOC_2_BUS_TIMEOUT_BASE 0x01e62000 211 #define PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000 212 #define PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000 213 214 215 216 #define PCNOC_3_BUS_TIMEOUT_BASE 0x01e63000 217 #define PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000 218 #define PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000 219 220 221 222 #define RRI_PREFETCH_REG_BASE 0x01e70000 223 #define RRI_PREFETCH_REG_BASE_SIZE 0x00010000 224 #define RRI_PREFETCH_REG_BASE_PHYS 0x01e70000 225 226 227 228 #define SYSTEM_NOC_BASE 0x01e80000 229 #define SYSTEM_NOC_BASE_SIZE 0x0000a000 230 #define SYSTEM_NOC_BASE_PHYS 0x01e80000 231 232 233 234 #define PC_NOC_BASE 0x01f00000 235 #define PC_NOC_BASE_SIZE 0x00003880 236 #define PC_NOC_BASE_PHYS 0x01f00000 237 238 239 240 #define WLAON_WL_AON_REG_BASE 0x01f80000 241 #define WLAON_WL_AON_REG_BASE_SIZE 0x000007c8 242 #define WLAON_WL_AON_REG_BASE_PHYS 0x01f80000 243 244 245 246 #define SYSPM_SYSPM_REG_BASE 0x01f82000 247 #define SYSPM_SYSPM_REG_BASE_SIZE 0x00001000 248 #define SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000 249 250 251 252 #define PMU_WLAN_PMU_TOP_BASE 0x01f88000 253 #define PMU_WLAN_PMU_TOP_BASE_SIZE 0x00000340 254 #define PMU_WLAN_PMU_TOP_BASE_PHYS 0x01f88000 255 256 257 258 #define PMU_NOC_BASE 0x01f8a000 259 #define PMU_NOC_BASE_SIZE 0x00000080 260 #define PMU_NOC_BASE_PHYS 0x01f8a000 261 262 263 264 #define PCIE_ATU_REGION_BASE 0x04000000 265 #define PCIE_ATU_REGION_BASE_SIZE 0x100000000 266 #define PCIE_ATU_REGION_BASE_PHYS 0x04000000 267 268 269 270 #define PCIE_ATU_REGION_SIZE_BASE 0x40000000 271 #define PCIE_ATU_REGION_SIZE_BASE_SIZE 0x100000000 272 #define PCIE_ATU_REGION_SIZE_BASE_PHYS 0x40000000 273 274 275 276 #define PCIE_ATU_REGION_END_BASE 0x43ffffff 277 #define PCIE_ATU_REGION_END_BASE_SIZE 0x100000000 278 #define PCIE_ATU_REGION_END_BASE_PHYS 0x43ffffff 279 280 281 #endif 282