1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _RECEIVE_USER_INFO_H_ 31 #define _RECEIVE_USER_INFO_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #define NUM_OF_DWORDS_RECEIVE_USER_INFO 12 36 37 38 struct receive_user_info { 39 uint32_t phy_ppdu_id : 16, 40 user_rssi : 8, 41 pkt_type : 4, 42 stbc : 1, 43 reception_type : 3; 44 uint32_t rate_mcs : 4, 45 sgi : 2, 46 reserved_1a : 2, 47 mimo_ss_bitmap : 8, 48 receive_bandwidth : 3, 49 reserved_1b : 5, 50 dl_ofdma_user_index : 8; 51 uint32_t dl_ofdma_content_channel : 1, 52 reserved_2a : 7, 53 nss : 3, 54 stream_offset : 3, 55 sta_dcm : 1, 56 ldpc : 1, 57 ru_type_80_0 : 4, 58 ru_type_80_1 : 4, 59 ru_type_80_2 : 4, 60 ru_type_80_3 : 4; 61 uint32_t ru_start_index_80_0 : 6, 62 reserved_3a : 2, 63 ru_start_index_80_1 : 6, 64 reserved_3b : 2, 65 ru_start_index_80_2 : 6, 66 reserved_3c : 2, 67 ru_start_index_80_3 : 6, 68 reserved_3d : 2; 69 uint32_t user_fd_rssi_ss0 : 32; 70 uint32_t user_fd_rssi_ss1 : 32; 71 uint32_t user_fd_rssi_ss2 : 32; 72 uint32_t user_fd_rssi_ss3 : 32; 73 uint32_t user_fd_rssi_ss4 : 32; 74 uint32_t user_fd_rssi_ss5 : 32; 75 uint32_t user_fd_rssi_ss6 : 32; 76 uint32_t user_fd_rssi_ss7 : 32; 77 }; 78 79 80 81 82 #define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000 83 #define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0 84 #define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15 85 #define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff 86 87 88 89 90 #define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000 91 #define RECEIVE_USER_INFO_USER_RSSI_LSB 16 92 #define RECEIVE_USER_INFO_USER_RSSI_MSB 23 93 #define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000 94 95 96 97 98 #define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000 99 #define RECEIVE_USER_INFO_PKT_TYPE_LSB 24 100 #define RECEIVE_USER_INFO_PKT_TYPE_MSB 27 101 #define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000 102 103 104 105 106 #define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000 107 #define RECEIVE_USER_INFO_STBC_LSB 28 108 #define RECEIVE_USER_INFO_STBC_MSB 28 109 #define RECEIVE_USER_INFO_STBC_MASK 0x10000000 110 111 112 113 114 #define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000 115 #define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29 116 #define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31 117 #define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000 118 119 120 121 122 #define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004 123 #define RECEIVE_USER_INFO_RATE_MCS_LSB 0 124 #define RECEIVE_USER_INFO_RATE_MCS_MSB 3 125 #define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000000f 126 127 128 129 130 #define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004 131 #define RECEIVE_USER_INFO_SGI_LSB 4 132 #define RECEIVE_USER_INFO_SGI_MSB 5 133 #define RECEIVE_USER_INFO_SGI_MASK 0x00000030 134 135 136 137 138 #define RECEIVE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 139 #define RECEIVE_USER_INFO_RESERVED_1A_LSB 6 140 #define RECEIVE_USER_INFO_RESERVED_1A_MSB 7 141 #define RECEIVE_USER_INFO_RESERVED_1A_MASK 0x000000c0 142 143 144 145 146 #define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004 147 #define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8 148 #define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15 149 #define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00 150 151 152 153 154 #define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004 155 #define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16 156 #define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18 157 #define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000 158 159 160 161 162 #define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004 163 #define RECEIVE_USER_INFO_RESERVED_1B_LSB 19 164 #define RECEIVE_USER_INFO_RESERVED_1B_MSB 23 165 #define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000 166 167 168 169 170 #define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 171 #define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24 172 #define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31 173 #define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000 174 175 176 177 178 #define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 179 #define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0 180 #define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0 181 #define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 182 183 184 185 186 #define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008 187 #define RECEIVE_USER_INFO_RESERVED_2A_LSB 1 188 #define RECEIVE_USER_INFO_RESERVED_2A_MSB 7 189 #define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x000000fe 190 191 192 193 194 #define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008 195 #define RECEIVE_USER_INFO_NSS_LSB 8 196 #define RECEIVE_USER_INFO_NSS_MSB 10 197 #define RECEIVE_USER_INFO_NSS_MASK 0x00000700 198 199 200 201 202 #define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008 203 #define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11 204 #define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13 205 #define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800 206 207 208 209 210 #define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008 211 #define RECEIVE_USER_INFO_STA_DCM_LSB 14 212 #define RECEIVE_USER_INFO_STA_DCM_MSB 14 213 #define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000 214 215 216 217 218 #define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008 219 #define RECEIVE_USER_INFO_LDPC_LSB 15 220 #define RECEIVE_USER_INFO_LDPC_MSB 15 221 #define RECEIVE_USER_INFO_LDPC_MASK 0x00008000 222 223 224 225 226 #define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008 227 #define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16 228 #define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19 229 #define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000 230 231 232 233 234 #define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008 235 #define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20 236 #define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23 237 #define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000 238 239 240 241 242 #define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008 243 #define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24 244 #define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27 245 #define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000 246 247 248 249 250 #define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008 251 #define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28 252 #define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31 253 #define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000 254 255 256 257 258 #define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c 259 #define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0 260 #define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5 261 #define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f 262 263 264 265 266 #define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c 267 #define RECEIVE_USER_INFO_RESERVED_3A_LSB 6 268 #define RECEIVE_USER_INFO_RESERVED_3A_MSB 7 269 #define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0 270 271 272 273 274 #define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c 275 #define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8 276 #define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13 277 #define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00 278 279 280 281 282 #define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c 283 #define RECEIVE_USER_INFO_RESERVED_3B_LSB 14 284 #define RECEIVE_USER_INFO_RESERVED_3B_MSB 15 285 #define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000 286 287 288 289 290 #define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c 291 #define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16 292 #define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21 293 #define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000 294 295 296 297 298 #define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c 299 #define RECEIVE_USER_INFO_RESERVED_3C_LSB 22 300 #define RECEIVE_USER_INFO_RESERVED_3C_MSB 23 301 #define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000 302 303 304 305 306 #define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c 307 #define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24 308 #define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29 309 #define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000 310 311 312 313 314 #define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c 315 #define RECEIVE_USER_INFO_RESERVED_3D_LSB 30 316 #define RECEIVE_USER_INFO_RESERVED_3D_MSB 31 317 #define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000 318 319 320 321 322 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS0_OFFSET 0x00000010 323 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS0_LSB 0 324 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS0_MSB 31 325 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS0_MASK 0xffffffff 326 327 328 329 330 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS1_OFFSET 0x00000014 331 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS1_LSB 0 332 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS1_MSB 31 333 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS1_MASK 0xffffffff 334 335 336 337 338 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS2_OFFSET 0x00000018 339 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS2_LSB 0 340 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS2_MSB 31 341 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS2_MASK 0xffffffff 342 343 344 345 346 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS3_OFFSET 0x0000001c 347 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS3_LSB 0 348 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS3_MSB 31 349 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS3_MASK 0xffffffff 350 351 352 353 354 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS4_OFFSET 0x00000020 355 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS4_LSB 0 356 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS4_MSB 31 357 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS4_MASK 0xffffffff 358 359 360 361 362 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS5_OFFSET 0x00000024 363 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS5_LSB 0 364 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS5_MSB 31 365 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS5_MASK 0xffffffff 366 367 368 369 370 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS6_OFFSET 0x00000028 371 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS6_LSB 0 372 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS6_MSB 31 373 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS6_MASK 0xffffffff 374 375 376 377 378 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS7_OFFSET 0x0000002c 379 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS7_LSB 0 380 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS7_MSB 31 381 #define RECEIVE_USER_INFO_USER_FD_RSSI_SS7_MASK 0xffffffff 382 383 384 385 #endif 386