1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _REO_FLUSH_CACHE_H_ 31 #define _REO_FLUSH_CACHE_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #include "uniform_reo_cmd_header.h" 36 #define NUM_OF_DWORDS_REO_FLUSH_CACHE 10 37 38 #define NUM_OF_QWORDS_REO_FLUSH_CACHE 5 39 40 41 struct reo_flush_cache { 42 struct uniform_reo_cmd_header cmd_header; 43 uint32_t flush_addr_31_0 : 32; 44 uint32_t flush_addr_39_32 : 8, 45 forward_all_mpdus_in_queue : 1, 46 release_cache_block_index : 1, 47 cache_block_resource_index : 2, 48 flush_without_invalidate : 1, 49 block_cache_usage_after_flush : 1, 50 flush_entire_cache : 1, 51 flush_queue_1k_desc : 1, 52 reserved_2b : 16; 53 uint32_t reserved_3a : 32; 54 uint32_t reserved_4a : 32; 55 uint32_t reserved_5a : 32; 56 uint32_t reserved_6a : 32; 57 uint32_t reserved_7a : 32; 58 uint32_t reserved_8a : 32; 59 uint32_t tlv64_padding : 32; 60 }; 61 62 63 64 65 66 67 68 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 69 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 70 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 71 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 72 73 74 75 76 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 77 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 78 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 79 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 80 81 82 83 84 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 85 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 86 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 87 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 88 89 90 91 92 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000 93 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32 94 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63 95 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000 96 97 98 99 100 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008 101 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0 102 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7 103 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff 104 105 106 107 108 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008 109 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 110 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8 111 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100 112 113 114 115 116 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008 117 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9 118 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9 119 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200 120 121 122 123 124 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 125 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 126 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11 127 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00 128 129 130 131 132 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008 133 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12 134 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12 135 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000 136 137 138 139 140 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 141 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 142 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13 143 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000 144 145 146 147 148 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008 149 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14 150 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14 151 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000 152 153 154 155 156 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 157 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15 158 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15 159 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000 160 161 162 163 164 #define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008 165 #define REO_FLUSH_CACHE_RESERVED_2B_LSB 16 166 #define REO_FLUSH_CACHE_RESERVED_2B_MSB 31 167 #define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000 168 169 170 171 172 #define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 173 #define REO_FLUSH_CACHE_RESERVED_3A_LSB 32 174 #define REO_FLUSH_CACHE_RESERVED_3A_MSB 63 175 #define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000 176 177 178 179 180 #define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 181 #define REO_FLUSH_CACHE_RESERVED_4A_LSB 0 182 #define REO_FLUSH_CACHE_RESERVED_4A_MSB 31 183 #define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff 184 185 186 187 188 #define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 189 #define REO_FLUSH_CACHE_RESERVED_5A_LSB 32 190 #define REO_FLUSH_CACHE_RESERVED_5A_MSB 63 191 #define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000 192 193 194 195 196 #define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 197 #define REO_FLUSH_CACHE_RESERVED_6A_LSB 0 198 #define REO_FLUSH_CACHE_RESERVED_6A_MSB 31 199 #define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff 200 201 202 203 204 #define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 205 #define REO_FLUSH_CACHE_RESERVED_7A_LSB 32 206 #define REO_FLUSH_CACHE_RESERVED_7A_MSB 63 207 #define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000 208 209 210 211 212 #define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 213 #define REO_FLUSH_CACHE_RESERVED_8A_LSB 0 214 #define REO_FLUSH_CACHE_RESERVED_8A_MSB 31 215 #define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff 216 217 218 219 220 #define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 221 #define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32 222 #define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63 223 #define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 224 225 226 227 #endif 228