1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _REO_FLUSH_CACHE_STATUS_H_ 31 #define _REO_FLUSH_CACHE_STATUS_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #include "uniform_reo_status_header.h" 36 #define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 26 37 38 #define NUM_OF_QWORDS_REO_FLUSH_CACHE_STATUS 13 39 40 41 struct reo_flush_cache_status { 42 struct uniform_reo_status_header status_header; 43 uint32_t error_detected : 1, 44 block_error_details : 2, 45 reserved_2a : 5, 46 cache_controller_flush_status_hit : 1, 47 cache_controller_flush_status_desc_type : 3, 48 cache_controller_flush_status_client_id : 4, 49 cache_controller_flush_status_error : 2, 50 cache_controller_flush_count : 8, 51 flush_queue_1k_desc : 1, 52 reserved_2b : 5; 53 uint32_t reserved_3a : 32; 54 uint32_t reserved_4a : 32; 55 uint32_t reserved_5a : 32; 56 uint32_t reserved_6a : 32; 57 uint32_t reserved_7a : 32; 58 uint32_t reserved_8a : 32; 59 uint32_t reserved_9a : 32; 60 uint32_t reserved_10a : 32; 61 uint32_t reserved_11a : 32; 62 uint32_t reserved_12a : 32; 63 uint32_t reserved_13a : 32; 64 uint32_t reserved_14a : 32; 65 uint32_t reserved_15a : 32; 66 uint32_t reserved_16a : 32; 67 uint32_t reserved_17a : 32; 68 uint32_t reserved_18a : 32; 69 uint32_t reserved_19a : 32; 70 uint32_t reserved_20a : 32; 71 uint32_t reserved_21a : 32; 72 uint32_t reserved_22a : 32; 73 uint32_t reserved_23a : 32; 74 uint32_t reserved_24a : 32; 75 uint32_t reserved_25a : 28, 76 looping_count : 4; 77 }; 78 79 80 81 82 83 84 85 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 86 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 87 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 88 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 89 90 91 92 93 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 94 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 95 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 96 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 97 98 99 100 101 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 102 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 103 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 104 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 105 106 107 108 109 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 110 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 111 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 112 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 113 114 115 116 117 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 118 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 119 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 120 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 121 122 123 124 125 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 126 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0 127 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0 128 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 129 130 131 132 133 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000000000008 134 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1 135 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2 136 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x0000000000000006 137 138 139 140 141 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 142 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3 143 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7 144 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x00000000000000f8 145 146 147 148 149 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000000000008 150 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 151 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8 152 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x0000000000000100 153 154 155 156 157 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000000000008 158 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 159 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11 160 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x0000000000000e00 161 162 163 164 165 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000000000008 166 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 167 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15 168 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x000000000000f000 169 170 171 172 173 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000000000008 174 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 175 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17 176 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x0000000000030000 177 178 179 180 181 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000000000008 182 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 183 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25 184 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x0000000003fc0000 185 186 187 188 189 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 190 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26 191 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26 192 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x0000000004000000 193 194 195 196 197 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000000000008 198 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27 199 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31 200 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0x00000000f8000000 201 202 203 204 205 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 206 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 32 207 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 63 208 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 209 210 211 212 213 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 214 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0 215 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31 216 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 217 218 219 220 221 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 222 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 32 223 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 63 224 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 225 226 227 228 229 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 230 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0 231 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31 232 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 233 234 235 236 237 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 238 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 32 239 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 63 240 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 241 242 243 244 245 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 246 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0 247 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31 248 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 249 250 251 252 253 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 254 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 32 255 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 63 256 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 257 258 259 260 261 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 262 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0 263 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31 264 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 265 266 267 268 269 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 270 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 32 271 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 63 272 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 273 274 275 276 277 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 278 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0 279 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31 280 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 281 282 283 284 285 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 286 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 32 287 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 63 288 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 289 290 291 292 293 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 294 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0 295 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31 296 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 297 298 299 300 301 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 302 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 32 303 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 63 304 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 305 306 307 308 309 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 310 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0 311 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31 312 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 313 314 315 316 317 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 318 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 32 319 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 63 320 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 321 322 323 324 325 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 326 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0 327 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31 328 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 329 330 331 332 333 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 334 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 32 335 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 63 336 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 337 338 339 340 341 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 342 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0 343 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31 344 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 345 346 347 348 349 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 350 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 32 351 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 63 352 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 353 354 355 356 357 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 358 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0 359 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31 360 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 361 362 363 364 365 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 366 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 32 367 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 63 368 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 369 370 371 372 373 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 374 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0 375 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31 376 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 377 378 379 380 381 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 382 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 32 383 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 59 384 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 385 386 387 388 389 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 390 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 60 391 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 63 392 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 393 394 395 396 #endif 397