1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _REO_FLUSH_QUEUE_H_ 31 #define _REO_FLUSH_QUEUE_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #include "uniform_reo_cmd_header.h" 36 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10 37 38 #define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5 39 40 41 struct reo_flush_queue { 42 struct uniform_reo_cmd_header cmd_header; 43 uint32_t flush_desc_addr_31_0 : 32; 44 uint32_t flush_desc_addr_39_32 : 8, 45 block_desc_addr_usage_after_flush : 1, 46 block_resource_index : 2, 47 invalidate_queue_and_flush : 1, 48 reserved_2a : 20; 49 uint32_t reserved_3a : 32; 50 uint32_t reserved_4a : 32; 51 uint32_t reserved_5a : 32; 52 uint32_t reserved_6a : 32; 53 uint32_t reserved_7a : 32; 54 uint32_t reserved_8a : 32; 55 uint32_t tlv64_padding : 32; 56 }; 57 58 59 60 61 62 63 64 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 65 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 66 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 67 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 68 69 70 71 72 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 73 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 74 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 75 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 76 77 78 79 80 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 81 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 82 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 83 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 84 85 86 87 88 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x0000000000000000 89 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 32 90 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 63 91 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff00000000 92 93 94 95 96 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x0000000000000008 97 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0 98 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7 99 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x00000000000000ff 100 101 102 103 104 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 105 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 106 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8 107 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x0000000000000100 108 109 110 111 112 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 113 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9 114 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10 115 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000600 116 117 118 119 120 #define REO_FLUSH_QUEUE_INVALIDATE_QUEUE_AND_FLUSH_OFFSET 0x0000000000000008 121 #define REO_FLUSH_QUEUE_INVALIDATE_QUEUE_AND_FLUSH_LSB 11 122 #define REO_FLUSH_QUEUE_INVALIDATE_QUEUE_AND_FLUSH_MSB 11 123 #define REO_FLUSH_QUEUE_INVALIDATE_QUEUE_AND_FLUSH_MASK 0x0000000000000800 124 125 126 127 128 #define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x0000000000000008 129 #define REO_FLUSH_QUEUE_RESERVED_2A_LSB 12 130 #define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31 131 #define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0x00000000fffff000 132 133 134 135 136 #define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000000000008 137 #define REO_FLUSH_QUEUE_RESERVED_3A_LSB 32 138 #define REO_FLUSH_QUEUE_RESERVED_3A_MSB 63 139 #define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff00000000 140 141 142 143 144 #define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 145 #define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0 146 #define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31 147 #define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0x00000000ffffffff 148 149 150 151 152 #define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x0000000000000010 153 #define REO_FLUSH_QUEUE_RESERVED_5A_LSB 32 154 #define REO_FLUSH_QUEUE_RESERVED_5A_MSB 63 155 #define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff00000000 156 157 158 159 160 #define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x0000000000000018 161 #define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0 162 #define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31 163 #define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0x00000000ffffffff 164 165 166 167 168 #define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000000000000018 169 #define REO_FLUSH_QUEUE_RESERVED_7A_LSB 32 170 #define REO_FLUSH_QUEUE_RESERVED_7A_MSB 63 171 #define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff00000000 172 173 174 175 176 #define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x0000000000000020 177 #define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0 178 #define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31 179 #define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0x00000000ffffffff 180 181 182 183 184 #define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 185 #define REO_FLUSH_QUEUE_TLV64_PADDING_LSB 32 186 #define REO_FLUSH_QUEUE_TLV64_PADDING_MSB 63 187 #define REO_FLUSH_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 188 189 190 191 #endif 192