1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _RX_ATTENTION_H_ 31 #define _RX_ATTENTION_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #define NUM_OF_DWORDS_RX_ATTENTION 4 36 37 #define NUM_OF_QWORDS_RX_ATTENTION 2 38 39 40 struct rx_attention { 41 uint32_t rxpcu_mpdu_filter_in_category : 2, 42 sw_frame_group_id : 7, 43 reserved_0 : 7, 44 phy_ppdu_id : 16; 45 uint32_t first_mpdu : 1, 46 reserved_1a : 1, 47 mcast_bcast : 1, 48 ast_index_not_found : 1, 49 ast_index_timeout : 1, 50 power_mgmt : 1, 51 non_qos : 1, 52 null_data : 1, 53 mgmt_type : 1, 54 ctrl_type : 1, 55 more_data : 1, 56 eosp : 1, 57 a_msdu_error : 1, 58 fragment_flag : 1, 59 order : 1, 60 cce_match : 1, 61 overflow_err : 1, 62 msdu_length_err : 1, 63 tcp_udp_chksum_fail : 1, 64 ip_chksum_fail : 1, 65 sa_idx_invalid : 1, 66 da_idx_invalid : 1, 67 reserved_1b : 1, 68 rx_in_tx_decrypt_byp : 1, 69 encrypt_required : 1, 70 directed : 1, 71 buffer_fragment : 1, 72 mpdu_length_err : 1, 73 tkip_mic_err : 1, 74 decrypt_err : 1, 75 unencrypted_frame_err : 1, 76 fcs_err : 1; 77 uint32_t flow_idx_timeout : 1, 78 flow_idx_invalid : 1, 79 wifi_parser_error : 1, 80 amsdu_parser_error : 1, 81 sa_idx_timeout : 1, 82 da_idx_timeout : 1, 83 msdu_limit_error : 1, 84 da_is_valid : 1, 85 da_is_mcbc : 1, 86 sa_is_valid : 1, 87 decrypt_status_code : 3, 88 rx_bitmap_not_updated : 1, 89 reserved_2 : 17, 90 msdu_done : 1; 91 uint32_t tlv64_padding : 32; 92 }; 93 94 95 96 97 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 98 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 99 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 100 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 101 102 103 104 105 #define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 106 #define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 107 #define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 108 #define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 109 110 111 112 113 #define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000 114 #define RX_ATTENTION_RESERVED_0_LSB 9 115 #define RX_ATTENTION_RESERVED_0_MSB 15 116 #define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00 117 118 119 120 121 #define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000 122 #define RX_ATTENTION_PHY_PPDU_ID_LSB 16 123 #define RX_ATTENTION_PHY_PPDU_ID_MSB 31 124 #define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000 125 126 127 128 129 #define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000 130 #define RX_ATTENTION_FIRST_MPDU_LSB 32 131 #define RX_ATTENTION_FIRST_MPDU_MSB 32 132 #define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000 133 134 135 136 137 #define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000 138 #define RX_ATTENTION_RESERVED_1A_LSB 33 139 #define RX_ATTENTION_RESERVED_1A_MSB 33 140 #define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000 141 142 143 144 145 #define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000 146 #define RX_ATTENTION_MCAST_BCAST_LSB 34 147 #define RX_ATTENTION_MCAST_BCAST_MSB 34 148 #define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000 149 150 151 152 153 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000 154 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35 155 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35 156 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000 157 158 159 160 161 #define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000 162 #define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36 163 #define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36 164 #define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000 165 166 167 168 169 #define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000 170 #define RX_ATTENTION_POWER_MGMT_LSB 37 171 #define RX_ATTENTION_POWER_MGMT_MSB 37 172 #define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000 173 174 175 176 177 #define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000 178 #define RX_ATTENTION_NON_QOS_LSB 38 179 #define RX_ATTENTION_NON_QOS_MSB 38 180 #define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000 181 182 183 184 185 #define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000 186 #define RX_ATTENTION_NULL_DATA_LSB 39 187 #define RX_ATTENTION_NULL_DATA_MSB 39 188 #define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000 189 190 191 192 193 #define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000 194 #define RX_ATTENTION_MGMT_TYPE_LSB 40 195 #define RX_ATTENTION_MGMT_TYPE_MSB 40 196 #define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000 197 198 199 200 201 #define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000 202 #define RX_ATTENTION_CTRL_TYPE_LSB 41 203 #define RX_ATTENTION_CTRL_TYPE_MSB 41 204 #define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000 205 206 207 208 209 #define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000 210 #define RX_ATTENTION_MORE_DATA_LSB 42 211 #define RX_ATTENTION_MORE_DATA_MSB 42 212 #define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000 213 214 215 216 217 #define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000 218 #define RX_ATTENTION_EOSP_LSB 43 219 #define RX_ATTENTION_EOSP_MSB 43 220 #define RX_ATTENTION_EOSP_MASK 0x0000080000000000 221 222 223 224 225 #define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000 226 #define RX_ATTENTION_A_MSDU_ERROR_LSB 44 227 #define RX_ATTENTION_A_MSDU_ERROR_MSB 44 228 #define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000 229 230 231 232 233 #define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000 234 #define RX_ATTENTION_FRAGMENT_FLAG_LSB 45 235 #define RX_ATTENTION_FRAGMENT_FLAG_MSB 45 236 #define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000 237 238 239 240 241 #define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000 242 #define RX_ATTENTION_ORDER_LSB 46 243 #define RX_ATTENTION_ORDER_MSB 46 244 #define RX_ATTENTION_ORDER_MASK 0x0000400000000000 245 246 247 248 249 #define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000 250 #define RX_ATTENTION_CCE_MATCH_LSB 47 251 #define RX_ATTENTION_CCE_MATCH_MSB 47 252 #define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000 253 254 255 256 257 #define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000 258 #define RX_ATTENTION_OVERFLOW_ERR_LSB 48 259 #define RX_ATTENTION_OVERFLOW_ERR_MSB 48 260 #define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000 261 262 263 264 265 #define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 266 #define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49 267 #define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49 268 #define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000 269 270 271 272 273 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000 274 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50 275 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50 276 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000 277 278 279 280 281 #define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000 282 #define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51 283 #define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51 284 #define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000 285 286 287 288 289 #define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000 290 #define RX_ATTENTION_SA_IDX_INVALID_LSB 52 291 #define RX_ATTENTION_SA_IDX_INVALID_MSB 52 292 #define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000 293 294 295 296 297 #define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000 298 #define RX_ATTENTION_DA_IDX_INVALID_LSB 53 299 #define RX_ATTENTION_DA_IDX_INVALID_MSB 53 300 #define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000 301 302 303 304 305 #define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000 306 #define RX_ATTENTION_RESERVED_1B_LSB 54 307 #define RX_ATTENTION_RESERVED_1B_MSB 54 308 #define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000 309 310 311 312 313 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 314 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55 315 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55 316 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000 317 318 319 320 321 #define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000 322 #define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56 323 #define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56 324 #define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000 325 326 327 328 329 #define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000 330 #define RX_ATTENTION_DIRECTED_LSB 57 331 #define RX_ATTENTION_DIRECTED_MSB 57 332 #define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000 333 334 335 336 337 #define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000 338 #define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58 339 #define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58 340 #define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000 341 342 343 344 345 #define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 346 #define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59 347 #define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59 348 #define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000 349 350 351 352 353 #define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000 354 #define RX_ATTENTION_TKIP_MIC_ERR_LSB 60 355 #define RX_ATTENTION_TKIP_MIC_ERR_MSB 60 356 #define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000 357 358 359 360 361 #define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000 362 #define RX_ATTENTION_DECRYPT_ERR_LSB 61 363 #define RX_ATTENTION_DECRYPT_ERR_MSB 61 364 #define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000 365 366 367 368 369 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 370 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62 371 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62 372 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000 373 374 375 376 377 #define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000 378 #define RX_ATTENTION_FCS_ERR_LSB 63 379 #define RX_ATTENTION_FCS_ERR_MSB 63 380 #define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000 381 382 383 384 385 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008 386 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 387 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 388 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001 389 390 391 392 393 #define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008 394 #define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 395 #define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 396 #define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002 397 398 399 400 401 #define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008 402 #define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 403 #define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 404 #define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004 405 406 407 408 409 #define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008 410 #define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 411 #define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 412 #define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008 413 414 415 416 417 #define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008 418 #define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 419 #define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 420 #define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010 421 422 423 424 425 #define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008 426 #define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 427 #define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 428 #define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020 429 430 431 432 433 #define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008 434 #define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 435 #define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 436 #define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040 437 438 439 440 441 #define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008 442 #define RX_ATTENTION_DA_IS_VALID_LSB 7 443 #define RX_ATTENTION_DA_IS_VALID_MSB 7 444 #define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080 445 446 447 448 449 #define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008 450 #define RX_ATTENTION_DA_IS_MCBC_LSB 8 451 #define RX_ATTENTION_DA_IS_MCBC_MSB 8 452 #define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100 453 454 455 456 457 #define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008 458 #define RX_ATTENTION_SA_IS_VALID_LSB 9 459 #define RX_ATTENTION_SA_IS_VALID_MSB 9 460 #define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200 461 462 463 464 465 #define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008 466 #define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 467 #define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 468 #define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00 469 470 471 472 473 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008 474 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 475 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 476 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000 477 478 479 480 481 #define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008 482 #define RX_ATTENTION_RESERVED_2_LSB 14 483 #define RX_ATTENTION_RESERVED_2_MSB 30 484 #define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000 485 486 487 488 489 #define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008 490 #define RX_ATTENTION_MSDU_DONE_LSB 31 491 #define RX_ATTENTION_MSDU_DONE_MSB 31 492 #define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000 493 494 495 496 497 #define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008 498 #define RX_ATTENTION_TLV64_PADDING_LSB 32 499 #define RX_ATTENTION_TLV64_PADDING_MSB 63 500 #define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000 501 502 503 504 #endif 505