xref: /wlan-driver/fw-api/hw/kiwi/v1/rx_mpdu_desc_info.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /*
3  * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 
21 
22 
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25 
26 
27 
28 
29 
30 #ifndef _RX_MPDU_DESC_INFO_H_
31 #define _RX_MPDU_DESC_INFO_H_
32 #if !defined(__ASSEMBLER__)
33 #endif
34 
35 #define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2
36 
37 
38 struct rx_mpdu_desc_info {
39 	     uint32_t msdu_count                                              :  8,
40 		      fragment_flag                                           :  1,
41 		      mpdu_retry_bit                                          :  1,
42 		      ampdu_flag                                              :  1,
43 		      bar_frame                                               :  1,
44 		      pn_fields_contain_valid_info                            :  1,
45 		      raw_mpdu                                                :  1,
46 		      more_fragment_flag                                      :  1,
47 		      vdev_id                                                 :  8,
48 		      reserved_0a                                             :  4,
49 		      mpdu_qos_control_valid                                  :  1,
50 		      tid                                                     :  4;
51 	     uint32_t peer_meta_data                                          : 32;
52 };
53 
54 
55 
56 
57 #define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET                                         0x00000000
58 #define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB                                            0
59 #define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB                                            7
60 #define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK                                           0x000000ff
61 
62 
63 
64 
65 #define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET                                      0x00000000
66 #define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB                                         8
67 #define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB                                         8
68 #define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK                                        0x00000100
69 
70 
71 
72 
73 #define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET                                     0x00000000
74 #define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB                                        9
75 #define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB                                        9
76 #define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK                                       0x00000200
77 
78 
79 
80 
81 #define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET                                         0x00000000
82 #define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB                                            10
83 #define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB                                            10
84 #define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK                                           0x00000400
85 
86 
87 
88 
89 #define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET                                          0x00000000
90 #define RX_MPDU_DESC_INFO_BAR_FRAME_LSB                                             11
91 #define RX_MPDU_DESC_INFO_BAR_FRAME_MSB                                             11
92 #define RX_MPDU_DESC_INFO_BAR_FRAME_MASK                                            0x00000800
93 
94 
95 
96 
97 #define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET                       0x00000000
98 #define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB                          12
99 #define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB                          12
100 #define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK                         0x00001000
101 
102 
103 
104 
105 #define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET                                           0x00000000
106 #define RX_MPDU_DESC_INFO_RAW_MPDU_LSB                                              13
107 #define RX_MPDU_DESC_INFO_RAW_MPDU_MSB                                              13
108 #define RX_MPDU_DESC_INFO_RAW_MPDU_MASK                                             0x00002000
109 
110 
111 
112 
113 #define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET                                 0x00000000
114 #define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB                                    14
115 #define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB                                    14
116 #define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK                                   0x00004000
117 
118 
119 
120 
121 #define RX_MPDU_DESC_INFO_VDEV_ID_OFFSET                                            0x00000000
122 #define RX_MPDU_DESC_INFO_VDEV_ID_LSB                                               15
123 #define RX_MPDU_DESC_INFO_VDEV_ID_MSB                                               22
124 #define RX_MPDU_DESC_INFO_VDEV_ID_MASK                                              0x007f8000
125 
126 
127 
128 
129 #define RX_MPDU_DESC_INFO_RESERVED_0A_OFFSET                                        0x00000000
130 #define RX_MPDU_DESC_INFO_RESERVED_0A_LSB                                           23
131 #define RX_MPDU_DESC_INFO_RESERVED_0A_MSB                                           26
132 #define RX_MPDU_DESC_INFO_RESERVED_0A_MASK                                          0x07800000
133 
134 
135 
136 
137 #define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET                             0x00000000
138 #define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB                                27
139 #define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB                                27
140 #define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK                               0x08000000
141 
142 
143 
144 
145 #define RX_MPDU_DESC_INFO_TID_OFFSET                                                0x00000000
146 #define RX_MPDU_DESC_INFO_TID_LSB                                                   28
147 #define RX_MPDU_DESC_INFO_TID_MSB                                                   31
148 #define RX_MPDU_DESC_INFO_TID_MASK                                                  0xf0000000
149 
150 
151 
152 
153 #define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET                                     0x00000004
154 #define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB                                        0
155 #define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB                                        31
156 #define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK                                       0xffffffff
157 
158 
159 
160 #endif
161