1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _RX_MPDU_END_H_ 31 #define _RX_MPDU_END_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #define NUM_OF_DWORDS_RX_MPDU_END 4 36 37 #define NUM_OF_QWORDS_RX_MPDU_END 2 38 39 40 struct rx_mpdu_end { 41 uint32_t rxpcu_mpdu_filter_in_category : 2, 42 sw_frame_group_id : 7, 43 reserved_0 : 7, 44 phy_ppdu_id : 16; 45 uint32_t reserved_1a : 11, 46 unsup_ktype_short_frame : 1, 47 rx_in_tx_decrypt_byp : 1, 48 overflow_err : 1, 49 mpdu_length_err : 1, 50 tkip_mic_err : 1, 51 decrypt_err : 1, 52 unencrypted_frame_err : 1, 53 pn_fields_contain_valid_info : 1, 54 fcs_err : 1, 55 msdu_length_err : 1, 56 rxdma0_destination_ring : 3, 57 rxdma1_destination_ring : 3, 58 decrypt_status_code : 3, 59 rx_bitmap_not_updated : 1, 60 reserved_1b : 1; 61 uint32_t reserved_2a : 15, 62 rxpcu_mgmt_sequence_nr_valid : 1, 63 rxpcu_mgmt_sequence_nr : 16; 64 uint32_t rxframe_assert_mlo_timestamp : 32; 65 }; 66 67 68 69 70 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 71 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 72 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 73 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 74 75 76 77 78 #define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 79 #define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 80 #define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 81 #define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 82 83 84 85 86 #define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 87 #define RX_MPDU_END_RESERVED_0_LSB 9 88 #define RX_MPDU_END_RESERVED_0_MSB 15 89 #define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 90 91 92 93 94 #define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 95 #define RX_MPDU_END_PHY_PPDU_ID_LSB 16 96 #define RX_MPDU_END_PHY_PPDU_ID_MSB 31 97 #define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 98 99 100 101 102 #define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 103 #define RX_MPDU_END_RESERVED_1A_LSB 32 104 #define RX_MPDU_END_RESERVED_1A_MSB 42 105 #define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff00000000 106 107 108 109 110 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 111 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 112 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 113 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 114 115 116 117 118 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 119 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 120 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 121 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 122 123 124 125 126 #define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 127 #define RX_MPDU_END_OVERFLOW_ERR_LSB 45 128 #define RX_MPDU_END_OVERFLOW_ERR_MSB 45 129 #define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 130 131 132 133 134 #define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 135 #define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 136 #define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 137 #define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 138 139 140 141 142 #define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 143 #define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 144 #define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 145 #define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 146 147 148 149 150 #define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 151 #define RX_MPDU_END_DECRYPT_ERR_LSB 48 152 #define RX_MPDU_END_DECRYPT_ERR_MSB 48 153 #define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 154 155 156 157 158 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 159 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 160 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 161 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 162 163 164 165 166 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 167 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 168 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 169 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 170 171 172 173 174 #define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 175 #define RX_MPDU_END_FCS_ERR_LSB 51 176 #define RX_MPDU_END_FCS_ERR_MSB 51 177 #define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 178 179 180 181 182 #define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 183 #define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 184 #define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 185 #define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 186 187 188 189 190 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x0000000000000000 191 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 53 192 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 55 193 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e0000000000000 194 195 196 197 198 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x0000000000000000 199 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 56 200 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 58 201 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x0700000000000000 202 203 204 205 206 #define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 207 #define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 208 #define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 209 #define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 210 211 212 213 214 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 215 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 216 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 217 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 218 219 220 221 222 #define RX_MPDU_END_RESERVED_1B_OFFSET 0x0000000000000000 223 #define RX_MPDU_END_RESERVED_1B_LSB 63 224 #define RX_MPDU_END_RESERVED_1B_MSB 63 225 #define RX_MPDU_END_RESERVED_1B_MASK 0x8000000000000000 226 227 228 229 230 #define RX_MPDU_END_RESERVED_2A_OFFSET 0x0000000000000008 231 #define RX_MPDU_END_RESERVED_2A_LSB 0 232 #define RX_MPDU_END_RESERVED_2A_MSB 14 233 #define RX_MPDU_END_RESERVED_2A_MASK 0x0000000000007fff 234 235 236 237 238 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 239 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 240 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 241 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 242 243 244 245 246 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 247 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 248 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 249 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 250 251 252 253 254 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_OFFSET 0x0000000000000008 255 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_LSB 32 256 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MSB 63 257 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MASK 0xffffffff00000000 258 259 260 261 #endif 262