1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _RX_MPDU_INFO_H_ 31 #define _RX_MPDU_INFO_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #include "rxpt_classify_info.h" 36 #define NUM_OF_DWORDS_RX_MPDU_INFO 30 37 38 39 struct rx_mpdu_info { 40 struct rxpt_classify_info rxpt_classify_info_details; 41 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 42 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 43 receive_queue_number : 16, 44 pre_delim_err_warning : 1, 45 first_delim_err : 1, 46 reserved_2a : 6; 47 uint32_t pn_31_0 : 32; 48 uint32_t pn_63_32 : 32; 49 uint32_t pn_95_64 : 32; 50 uint32_t pn_127_96 : 32; 51 uint32_t epd_en : 1, 52 all_frames_shall_be_encrypted : 1, 53 encrypt_type : 4, 54 wep_key_width_for_variable_key : 2, 55 mesh_sta : 2, 56 bssid_hit : 1, 57 bssid_number : 4, 58 tid : 4, 59 reserved_7a : 13; 60 uint32_t peer_meta_data : 32; 61 uint32_t rxpcu_mpdu_filter_in_category : 2, 62 sw_frame_group_id : 7, 63 ndp_frame : 1, 64 phy_err : 1, 65 phy_err_during_mpdu_header : 1, 66 protocol_version_err : 1, 67 ast_based_lookup_valid : 1, 68 ranging : 1, 69 reserved_9a : 1, 70 phy_ppdu_id : 16; 71 uint32_t ast_index : 16, 72 sw_peer_id : 16; 73 uint32_t mpdu_frame_control_valid : 1, 74 mpdu_duration_valid : 1, 75 mac_addr_ad1_valid : 1, 76 mac_addr_ad2_valid : 1, 77 mac_addr_ad3_valid : 1, 78 mac_addr_ad4_valid : 1, 79 mpdu_sequence_control_valid : 1, 80 mpdu_qos_control_valid : 1, 81 mpdu_ht_control_valid : 1, 82 frame_encryption_info_valid : 1, 83 mpdu_fragment_number : 4, 84 more_fragment_flag : 1, 85 reserved_11a : 1, 86 fr_ds : 1, 87 to_ds : 1, 88 encrypted : 1, 89 mpdu_retry : 1, 90 mpdu_sequence_number : 12; 91 uint32_t key_id_octet : 8, 92 new_peer_entry : 1, 93 decrypt_needed : 1, 94 decap_type : 2, 95 rx_insert_vlan_c_tag_padding : 1, 96 rx_insert_vlan_s_tag_padding : 1, 97 strip_vlan_c_tag_decap : 1, 98 strip_vlan_s_tag_decap : 1, 99 pre_delim_count : 12, 100 ampdu_flag : 1, 101 bar_frame : 1, 102 raw_mpdu : 1, 103 reserved_12 : 1; 104 uint32_t mpdu_length : 14, 105 first_mpdu : 1, 106 mcast_bcast : 1, 107 ast_index_not_found : 1, 108 ast_index_timeout : 1, 109 power_mgmt : 1, 110 non_qos : 1, 111 null_data : 1, 112 mgmt_type : 1, 113 ctrl_type : 1, 114 more_data : 1, 115 eosp : 1, 116 fragment_flag : 1, 117 order : 1, 118 u_apsd_trigger : 1, 119 encrypt_required : 1, 120 directed : 1, 121 amsdu_present : 1, 122 reserved_13 : 1; 123 uint32_t mpdu_frame_control_field : 16, 124 mpdu_duration_field : 16; 125 uint32_t mac_addr_ad1_31_0 : 32; 126 uint32_t mac_addr_ad1_47_32 : 16, 127 mac_addr_ad2_15_0 : 16; 128 uint32_t mac_addr_ad2_47_16 : 32; 129 uint32_t mac_addr_ad3_31_0 : 32; 130 uint32_t mac_addr_ad3_47_32 : 16, 131 mpdu_sequence_control_field : 16; 132 uint32_t mac_addr_ad4_31_0 : 32; 133 uint32_t mac_addr_ad4_47_32 : 16, 134 mpdu_qos_control_field : 16; 135 uint32_t mpdu_ht_control_field : 32; 136 uint32_t vdev_id : 8, 137 service_code : 9, 138 priority_valid : 1, 139 src_info : 12, 140 reserved_23a : 1, 141 multi_link_addr_ad1_ad2_valid : 1; 142 uint32_t multi_link_addr_ad1_31_0 : 32; 143 uint32_t multi_link_addr_ad1_47_32 : 16, 144 multi_link_addr_ad2_15_0 : 16; 145 uint32_t multi_link_addr_ad2_47_16 : 32; 146 uint32_t reserved_27a : 32; 147 uint32_t reserved_28a : 32; 148 uint32_t reserved_29a : 32; 149 }; 150 151 152 153 154 155 156 157 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 158 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 159 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 160 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 161 162 163 164 165 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 166 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 167 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 168 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 169 170 171 172 173 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 174 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 175 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 176 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 177 178 179 180 181 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 182 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 183 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 184 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 185 186 187 188 189 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 190 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 191 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 192 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 193 194 195 196 197 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 198 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 199 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 200 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 201 202 203 204 205 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 206 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 207 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 208 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 209 210 211 212 213 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 214 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 215 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 216 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 217 218 219 220 221 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 222 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 223 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 224 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 225 226 227 228 229 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 230 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 231 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 232 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 233 234 235 236 237 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 238 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 239 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 240 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 241 242 243 244 245 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 246 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 247 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 248 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 249 250 251 252 253 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 254 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 255 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 256 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 257 258 259 260 261 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 262 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22 263 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 264 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffc00000 265 266 267 268 269 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 270 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 271 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 272 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 273 274 275 276 277 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 278 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 279 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 280 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 281 282 283 284 285 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 286 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 287 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 288 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 289 290 291 292 293 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 294 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 295 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 296 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 297 298 299 300 301 #define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x00000008 302 #define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 303 #define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 304 #define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 305 306 307 308 309 #define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x00000008 310 #define RX_MPDU_INFO_RESERVED_2A_LSB 26 311 #define RX_MPDU_INFO_RESERVED_2A_MSB 31 312 #define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 313 314 315 316 317 #define RX_MPDU_INFO_PN_31_0_OFFSET 0x0000000c 318 #define RX_MPDU_INFO_PN_31_0_LSB 0 319 #define RX_MPDU_INFO_PN_31_0_MSB 31 320 #define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff 321 322 323 324 325 #define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000010 326 #define RX_MPDU_INFO_PN_63_32_LSB 0 327 #define RX_MPDU_INFO_PN_63_32_MSB 31 328 #define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff 329 330 331 332 333 #define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000014 334 #define RX_MPDU_INFO_PN_95_64_LSB 0 335 #define RX_MPDU_INFO_PN_95_64_MSB 31 336 #define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff 337 338 339 340 341 #define RX_MPDU_INFO_PN_127_96_OFFSET 0x00000018 342 #define RX_MPDU_INFO_PN_127_96_LSB 0 343 #define RX_MPDU_INFO_PN_127_96_MSB 31 344 #define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff 345 346 347 348 349 #define RX_MPDU_INFO_EPD_EN_OFFSET 0x0000001c 350 #define RX_MPDU_INFO_EPD_EN_LSB 0 351 #define RX_MPDU_INFO_EPD_EN_MSB 0 352 #define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 353 354 355 356 357 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c 358 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 359 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 360 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 361 362 363 364 365 #define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x0000001c 366 #define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 367 #define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 368 #define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c 369 370 371 372 373 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c 374 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 375 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 376 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 377 378 379 380 381 #define RX_MPDU_INFO_MESH_STA_OFFSET 0x0000001c 382 #define RX_MPDU_INFO_MESH_STA_LSB 8 383 #define RX_MPDU_INFO_MESH_STA_MSB 9 384 #define RX_MPDU_INFO_MESH_STA_MASK 0x00000300 385 386 387 388 389 #define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x0000001c 390 #define RX_MPDU_INFO_BSSID_HIT_LSB 10 391 #define RX_MPDU_INFO_BSSID_HIT_MSB 10 392 #define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 393 394 395 396 397 #define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x0000001c 398 #define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 399 #define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 400 #define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 401 402 403 404 405 #define RX_MPDU_INFO_TID_OFFSET 0x0000001c 406 #define RX_MPDU_INFO_TID_LSB 15 407 #define RX_MPDU_INFO_TID_MSB 18 408 #define RX_MPDU_INFO_TID_MASK 0x00078000 409 410 411 412 413 #define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x0000001c 414 #define RX_MPDU_INFO_RESERVED_7A_LSB 19 415 #define RX_MPDU_INFO_RESERVED_7A_MSB 31 416 #define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 417 418 419 420 421 #define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000020 422 #define RX_MPDU_INFO_PEER_META_DATA_LSB 0 423 #define RX_MPDU_INFO_PEER_META_DATA_MSB 31 424 #define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff 425 426 427 428 429 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 430 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 431 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 432 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 433 434 435 436 437 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x00000024 438 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 439 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 440 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc 441 442 443 444 445 #define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x00000024 446 #define RX_MPDU_INFO_NDP_FRAME_LSB 9 447 #define RX_MPDU_INFO_NDP_FRAME_MSB 9 448 #define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 449 450 451 452 453 #define RX_MPDU_INFO_PHY_ERR_OFFSET 0x00000024 454 #define RX_MPDU_INFO_PHY_ERR_LSB 10 455 #define RX_MPDU_INFO_PHY_ERR_MSB 10 456 #define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 457 458 459 460 461 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 462 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 463 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 464 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 465 466 467 468 469 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 470 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 471 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 472 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 473 474 475 476 477 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 478 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 479 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 480 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 481 482 483 484 485 #define RX_MPDU_INFO_RANGING_OFFSET 0x00000024 486 #define RX_MPDU_INFO_RANGING_LSB 14 487 #define RX_MPDU_INFO_RANGING_MSB 14 488 #define RX_MPDU_INFO_RANGING_MASK 0x00004000 489 490 491 492 493 #define RX_MPDU_INFO_RESERVED_9A_OFFSET 0x00000024 494 #define RX_MPDU_INFO_RESERVED_9A_LSB 15 495 #define RX_MPDU_INFO_RESERVED_9A_MSB 15 496 #define RX_MPDU_INFO_RESERVED_9A_MASK 0x00008000 497 498 499 500 501 #define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x00000024 502 #define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 503 #define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 504 #define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 505 506 507 508 509 #define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 510 #define RX_MPDU_INFO_AST_INDEX_LSB 0 511 #define RX_MPDU_INFO_AST_INDEX_MSB 15 512 #define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff 513 514 515 516 517 #define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 518 #define RX_MPDU_INFO_SW_PEER_ID_LSB 16 519 #define RX_MPDU_INFO_SW_PEER_ID_MSB 31 520 #define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 521 522 523 524 525 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c 526 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 527 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 528 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 529 530 531 532 533 #define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x0000002c 534 #define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 535 #define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 536 #define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 537 538 539 540 541 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c 542 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 543 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 544 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 545 546 547 548 549 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c 550 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 551 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 552 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 553 554 555 556 557 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c 558 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 559 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 560 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 561 562 563 564 565 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c 566 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 567 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 568 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 569 570 571 572 573 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c 574 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 575 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 576 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 577 578 579 580 581 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c 582 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 583 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 584 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 585 586 587 588 589 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c 590 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 591 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 592 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 593 594 595 596 597 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c 598 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 599 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 600 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 601 602 603 604 605 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c 606 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 607 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 608 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 609 610 611 612 613 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c 614 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 615 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 616 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 617 618 619 620 621 #define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x0000002c 622 #define RX_MPDU_INFO_RESERVED_11A_LSB 15 623 #define RX_MPDU_INFO_RESERVED_11A_MSB 15 624 #define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000 625 626 627 628 629 #define RX_MPDU_INFO_FR_DS_OFFSET 0x0000002c 630 #define RX_MPDU_INFO_FR_DS_LSB 16 631 #define RX_MPDU_INFO_FR_DS_MSB 16 632 #define RX_MPDU_INFO_FR_DS_MASK 0x00010000 633 634 635 636 637 #define RX_MPDU_INFO_TO_DS_OFFSET 0x0000002c 638 #define RX_MPDU_INFO_TO_DS_LSB 17 639 #define RX_MPDU_INFO_TO_DS_MSB 17 640 #define RX_MPDU_INFO_TO_DS_MASK 0x00020000 641 642 643 644 645 #define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x0000002c 646 #define RX_MPDU_INFO_ENCRYPTED_LSB 18 647 #define RX_MPDU_INFO_ENCRYPTED_MSB 18 648 #define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 649 650 651 652 653 #define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x0000002c 654 #define RX_MPDU_INFO_MPDU_RETRY_LSB 19 655 #define RX_MPDU_INFO_MPDU_RETRY_MSB 19 656 #define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 657 658 659 660 661 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c 662 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 663 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 664 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 665 666 667 668 669 #define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 670 #define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 671 #define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 672 #define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff 673 674 675 676 677 #define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 678 #define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 679 #define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 680 #define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 681 682 683 684 685 #define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 686 #define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 687 #define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 688 #define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 689 690 691 692 693 #define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 694 #define RX_MPDU_INFO_DECAP_TYPE_LSB 10 695 #define RX_MPDU_INFO_DECAP_TYPE_MSB 11 696 #define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 697 698 699 700 701 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 702 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 703 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 704 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 705 706 707 708 709 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 710 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 711 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 712 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 713 714 715 716 717 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 718 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 719 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 720 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 721 722 723 724 725 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 726 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 727 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 728 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 729 730 731 732 733 #define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 734 #define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 735 #define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 736 #define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 737 738 739 740 741 #define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 742 #define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 743 #define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 744 #define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 745 746 747 748 749 #define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 750 #define RX_MPDU_INFO_BAR_FRAME_LSB 29 751 #define RX_MPDU_INFO_BAR_FRAME_MSB 29 752 #define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 753 754 755 756 757 #define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 758 #define RX_MPDU_INFO_RAW_MPDU_LSB 30 759 #define RX_MPDU_INFO_RAW_MPDU_MSB 30 760 #define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 761 762 763 764 765 #define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 766 #define RX_MPDU_INFO_RESERVED_12_LSB 31 767 #define RX_MPDU_INFO_RESERVED_12_MSB 31 768 #define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 769 770 771 772 773 #define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 774 #define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 775 #define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 776 #define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff 777 778 779 780 781 #define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 782 #define RX_MPDU_INFO_FIRST_MPDU_LSB 14 783 #define RX_MPDU_INFO_FIRST_MPDU_MSB 14 784 #define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 785 786 787 788 789 #define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 790 #define RX_MPDU_INFO_MCAST_BCAST_LSB 15 791 #define RX_MPDU_INFO_MCAST_BCAST_MSB 15 792 #define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 793 794 795 796 797 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 798 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 799 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 800 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 801 802 803 804 805 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 806 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 807 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 808 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 809 810 811 812 813 #define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 814 #define RX_MPDU_INFO_POWER_MGMT_LSB 18 815 #define RX_MPDU_INFO_POWER_MGMT_MSB 18 816 #define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 817 818 819 820 821 #define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 822 #define RX_MPDU_INFO_NON_QOS_LSB 19 823 #define RX_MPDU_INFO_NON_QOS_MSB 19 824 #define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 825 826 827 828 829 #define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 830 #define RX_MPDU_INFO_NULL_DATA_LSB 20 831 #define RX_MPDU_INFO_NULL_DATA_MSB 20 832 #define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 833 834 835 836 837 #define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 838 #define RX_MPDU_INFO_MGMT_TYPE_LSB 21 839 #define RX_MPDU_INFO_MGMT_TYPE_MSB 21 840 #define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 841 842 843 844 845 #define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 846 #define RX_MPDU_INFO_CTRL_TYPE_LSB 22 847 #define RX_MPDU_INFO_CTRL_TYPE_MSB 22 848 #define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 849 850 851 852 853 #define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 854 #define RX_MPDU_INFO_MORE_DATA_LSB 23 855 #define RX_MPDU_INFO_MORE_DATA_MSB 23 856 #define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 857 858 859 860 861 #define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 862 #define RX_MPDU_INFO_EOSP_LSB 24 863 #define RX_MPDU_INFO_EOSP_MSB 24 864 #define RX_MPDU_INFO_EOSP_MASK 0x01000000 865 866 867 868 869 #define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 870 #define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 871 #define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 872 #define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 873 874 875 876 877 #define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 878 #define RX_MPDU_INFO_ORDER_LSB 26 879 #define RX_MPDU_INFO_ORDER_MSB 26 880 #define RX_MPDU_INFO_ORDER_MASK 0x04000000 881 882 883 884 885 #define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 886 #define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 887 #define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 888 #define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 889 890 891 892 893 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 894 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 895 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 896 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 897 898 899 900 901 #define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 902 #define RX_MPDU_INFO_DIRECTED_LSB 29 903 #define RX_MPDU_INFO_DIRECTED_MSB 29 904 #define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 905 906 907 908 909 #define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 910 #define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 911 #define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 912 #define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 913 914 915 916 917 #define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 918 #define RX_MPDU_INFO_RESERVED_13_LSB 31 919 #define RX_MPDU_INFO_RESERVED_13_MSB 31 920 #define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 921 922 923 924 925 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 926 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 927 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 928 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 929 930 931 932 933 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 934 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 935 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 936 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 937 938 939 940 941 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 942 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 943 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 944 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff 945 946 947 948 949 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 950 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 951 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 952 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 953 954 955 956 957 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 958 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 959 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 960 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 961 962 963 964 965 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 966 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 967 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 968 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff 969 970 971 972 973 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 974 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 975 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 976 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff 977 978 979 980 981 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 982 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 983 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 984 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 985 986 987 988 989 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 990 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 991 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 992 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 993 994 995 996 997 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 998 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 999 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 1000 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff 1001 1002 1003 1004 1005 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 1006 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 1007 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 1008 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 1009 1010 1011 1012 1013 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 1014 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 1015 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 1016 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 1017 1018 1019 1020 1021 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 1022 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 1023 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 1024 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 1025 1026 1027 1028 1029 #define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c 1030 #define RX_MPDU_INFO_VDEV_ID_LSB 0 1031 #define RX_MPDU_INFO_VDEV_ID_MSB 7 1032 #define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff 1033 1034 1035 1036 1037 #define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c 1038 #define RX_MPDU_INFO_SERVICE_CODE_LSB 8 1039 #define RX_MPDU_INFO_SERVICE_CODE_MSB 16 1040 #define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 1041 1042 1043 1044 1045 #define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c 1046 #define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 1047 #define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 1048 #define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 1049 1050 1051 1052 1053 #define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c 1054 #define RX_MPDU_INFO_SRC_INFO_LSB 18 1055 #define RX_MPDU_INFO_SRC_INFO_MSB 29 1056 #define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 1057 1058 1059 1060 1061 #define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c 1062 #define RX_MPDU_INFO_RESERVED_23A_LSB 30 1063 #define RX_MPDU_INFO_RESERVED_23A_MSB 30 1064 #define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000 1065 1066 1067 1068 1069 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_OFFSET 0x0000005c 1070 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_LSB 31 1071 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_MSB 31 1072 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_MASK 0x80000000 1073 1074 1075 1076 1077 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x00000060 1078 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_LSB 0 1079 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_MSB 31 1080 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_MASK 0xffffffff 1081 1082 1083 1084 1085 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x00000064 1086 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_LSB 0 1087 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_MSB 15 1088 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff 1089 1090 1091 1092 1093 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x00000064 1094 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_LSB 16 1095 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_MSB 31 1096 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff0000 1097 1098 1099 1100 1101 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x00000068 1102 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_LSB 0 1103 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_MSB 31 1104 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_MASK 0xffffffff 1105 1106 1107 1108 1109 #define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c 1110 #define RX_MPDU_INFO_RESERVED_27A_LSB 0 1111 #define RX_MPDU_INFO_RESERVED_27A_MSB 31 1112 #define RX_MPDU_INFO_RESERVED_27A_MASK 0xffffffff 1113 1114 1115 1116 1117 #define RX_MPDU_INFO_RESERVED_28A_OFFSET 0x00000070 1118 #define RX_MPDU_INFO_RESERVED_28A_LSB 0 1119 #define RX_MPDU_INFO_RESERVED_28A_MSB 31 1120 #define RX_MPDU_INFO_RESERVED_28A_MASK 0xffffffff 1121 1122 1123 1124 1125 #define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 1126 #define RX_MPDU_INFO_RESERVED_29A_LSB 0 1127 #define RX_MPDU_INFO_RESERVED_29A_MSB 31 1128 #define RX_MPDU_INFO_RESERVED_29A_MASK 0xffffffff 1129 1130 1131 1132 #endif 1133