1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _RX_MSDU_DESC_INFO_H_ 31 #define _RX_MSDU_DESC_INFO_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 36 37 38 struct rx_msdu_desc_info { 39 uint32_t first_msdu_in_mpdu_flag : 1, 40 last_msdu_in_mpdu_flag : 1, 41 msdu_continuation : 1, 42 msdu_length : 14, 43 msdu_drop : 1, 44 sa_is_valid : 1, 45 da_is_valid : 1, 46 da_is_mcbc : 1, 47 l3_header_padding_msb : 1, 48 tcp_udp_chksum_fail : 1, 49 ip_chksum_fail : 1, 50 fr_ds : 1, 51 to_ds : 1, 52 intra_bss : 1, 53 dest_chip_id : 2, 54 reserved_0a : 3; 55 }; 56 57 58 59 60 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 61 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 62 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 63 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 64 65 66 67 68 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 69 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 70 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 71 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 72 73 74 75 76 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 77 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 78 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 79 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 80 81 82 83 84 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 85 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 86 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 87 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 88 89 90 91 92 #define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 93 #define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 94 #define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 95 #define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 96 97 98 99 100 #define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 101 #define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 102 #define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 103 #define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 104 105 106 107 108 #define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 109 #define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 110 #define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 111 #define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 112 113 114 115 116 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 117 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 118 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 119 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 120 121 122 123 124 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 125 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 126 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 127 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 128 129 130 131 132 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 133 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 134 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 135 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 136 137 138 139 140 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 141 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 142 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 143 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 144 145 146 147 148 #define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 149 #define RX_MSDU_DESC_INFO_FR_DS_LSB 24 150 #define RX_MSDU_DESC_INFO_FR_DS_MSB 24 151 #define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 152 153 154 155 156 #define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 157 #define RX_MSDU_DESC_INFO_TO_DS_LSB 25 158 #define RX_MSDU_DESC_INFO_TO_DS_MSB 25 159 #define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 160 161 162 163 164 #define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 165 #define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 166 #define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 167 #define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 168 169 170 171 172 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 173 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 174 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 175 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 176 177 178 179 180 #define RX_MSDU_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 181 #define RX_MSDU_DESC_INFO_RESERVED_0A_LSB 29 182 #define RX_MSDU_DESC_INFO_RESERVED_0A_MSB 31 183 #define RX_MSDU_DESC_INFO_RESERVED_0A_MASK 0xe0000000 184 185 186 187 #endif 188