1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _RX_MSDU_DETAILS_H_ 31 #define _RX_MSDU_DETAILS_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #include "rx_msdu_desc_info.h" 36 #include "rx_msdu_ext_desc_info.h" 37 #include "buffer_addr_info.h" 38 #define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 39 40 41 struct rx_msdu_details { 42 struct buffer_addr_info buffer_addr_info_details; 43 struct rx_msdu_desc_info rx_msdu_desc_info_details; 44 struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; 45 }; 46 47 48 49 50 51 52 53 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 54 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 55 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 56 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 57 58 59 60 61 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 62 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 63 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 64 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 65 66 67 68 69 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 70 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 71 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 72 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 73 74 75 76 77 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 78 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 79 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 80 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 81 82 83 84 85 86 87 88 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 89 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 90 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 91 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 92 93 94 95 96 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 97 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 98 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 99 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 100 101 102 103 104 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 105 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 106 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 107 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 108 109 110 111 112 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 113 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 114 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 115 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 116 117 118 119 120 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 121 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 122 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 123 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 124 125 126 127 128 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 129 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 130 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 131 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 132 133 134 135 136 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 137 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 138 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 139 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 140 141 142 143 144 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 145 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 146 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 147 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 148 149 150 151 152 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 153 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 154 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 155 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 156 157 158 159 160 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 161 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 162 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 163 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 164 165 166 167 168 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 169 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 170 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 171 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 172 173 174 175 176 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 177 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 178 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 179 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 180 181 182 183 184 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 185 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 186 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 187 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 188 189 190 191 192 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 193 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 194 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 195 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 196 197 198 199 200 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 201 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 202 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 203 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 204 205 206 207 208 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008 209 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 29 210 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 211 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xe0000000 212 213 214 215 216 217 218 219 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c 220 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 221 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 222 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 223 224 225 226 227 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c 228 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 229 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 230 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 231 232 233 234 235 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c 236 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 237 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 238 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 239 240 241 242 243 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c 244 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 245 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 246 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 247 248 249 250 251 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c 252 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 27 253 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 254 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf8000000 255 256 257 258 #endif 259