1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _RX_PPDU_START_H_ 31 #define _RX_PPDU_START_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #define NUM_OF_DWORDS_RX_PPDU_START 6 36 37 #define NUM_OF_QWORDS_RX_PPDU_START 3 38 39 40 struct rx_ppdu_start { 41 uint32_t phy_ppdu_id : 16, 42 preamble_time_to_rxframe : 8, 43 reserved_0a : 8; 44 uint32_t sw_phy_meta_data : 32; 45 uint32_t ppdu_start_timestamp_31_0 : 32; 46 uint32_t ppdu_start_timestamp_63_32 : 32; 47 uint32_t rxframe_assert_timestamp : 32; 48 uint32_t tlv64_padding : 32; 49 }; 50 51 52 53 54 #define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 55 #define RX_PPDU_START_PHY_PPDU_ID_LSB 0 56 #define RX_PPDU_START_PHY_PPDU_ID_MSB 15 57 #define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff 58 59 60 61 62 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 63 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 64 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 65 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 66 67 68 69 70 #define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 71 #define RX_PPDU_START_RESERVED_0A_LSB 24 72 #define RX_PPDU_START_RESERVED_0A_MSB 31 73 #define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 74 75 76 77 78 #define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 79 #define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 80 #define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 81 #define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 82 83 84 85 86 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 87 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 88 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 89 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff 90 91 92 93 94 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 95 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 96 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 97 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 98 99 100 101 102 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 103 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 104 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 105 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff 106 107 108 109 110 #define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 111 #define RX_PPDU_START_TLV64_PADDING_LSB 32 112 #define RX_PPDU_START_TLV64_PADDING_MSB 63 113 #define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 114 115 116 117 #endif 118