1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _TCL_DATA_CMD_H_ 31 #define _TCL_DATA_CMD_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #include "buffer_addr_info.h" 36 #define NUM_OF_DWORDS_TCL_DATA_CMD 8 37 38 39 struct tcl_data_cmd { 40 struct buffer_addr_info buf_addr_info; 41 uint32_t tcl_cmd_type : 1, 42 buf_or_ext_desc_type : 1, 43 bank_id : 6, 44 tx_notify_frame : 3, 45 header_length_read_sel : 1, 46 buffer_timestamp : 19, 47 buffer_timestamp_valid : 1; 48 uint32_t reserved_3a : 16, 49 tcl_cmd_number : 16; 50 uint32_t data_length : 16, 51 ipv4_checksum_en : 1, 52 udp_over_ipv4_checksum_en : 1, 53 udp_over_ipv6_checksum_en : 1, 54 tcp_over_ipv4_checksum_en : 1, 55 tcp_over_ipv6_checksum_en : 1, 56 to_fw : 1, 57 reserved_4a : 1, 58 packet_offset : 9; 59 uint32_t hlos_tid_overwrite : 1, 60 flow_override_enable : 1, 61 who_classify_info_sel : 2, 62 hlos_tid : 4, 63 flow_override : 1, 64 pmac_id : 2, 65 reserved_5a : 13, 66 vdev_id : 8; 67 uint32_t search_index : 20, 68 cache_set_num : 4, 69 index_lookup_override : 1, 70 reserved_6a : 7; 71 uint32_t reserved_7a : 20, 72 ring_id : 8, 73 looping_count : 4; 74 }; 75 76 77 78 79 80 81 82 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 83 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 84 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 85 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 86 87 88 89 90 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 91 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 92 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 93 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 94 95 96 97 98 #define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 99 #define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 100 #define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 101 #define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 102 103 104 105 106 #define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 107 #define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 108 #define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 109 #define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 110 111 112 113 114 #define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 115 #define TCL_DATA_CMD_TCL_CMD_TYPE_LSB 0 116 #define TCL_DATA_CMD_TCL_CMD_TYPE_MSB 0 117 #define TCL_DATA_CMD_TCL_CMD_TYPE_MASK 0x00000001 118 119 120 121 122 #define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 123 #define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 1 124 #define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB 1 125 #define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000002 126 127 128 129 130 #define TCL_DATA_CMD_BANK_ID_OFFSET 0x00000008 131 #define TCL_DATA_CMD_BANK_ID_LSB 2 132 #define TCL_DATA_CMD_BANK_ID_MSB 7 133 #define TCL_DATA_CMD_BANK_ID_MASK 0x000000fc 134 135 136 137 138 #define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET 0x00000008 139 #define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB 8 140 #define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB 10 141 #define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK 0x00000700 142 143 144 145 146 #define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET 0x00000008 147 #define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB 11 148 #define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB 11 149 #define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK 0x00000800 150 151 152 153 154 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000008 155 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB 12 156 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB 30 157 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK 0x7ffff000 158 159 160 161 162 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000008 163 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB 31 164 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB 31 165 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x80000000 166 167 168 169 170 #define TCL_DATA_CMD_RESERVED_3A_OFFSET 0x0000000c 171 #define TCL_DATA_CMD_RESERVED_3A_LSB 0 172 #define TCL_DATA_CMD_RESERVED_3A_MSB 15 173 #define TCL_DATA_CMD_RESERVED_3A_MASK 0x0000ffff 174 175 176 177 178 #define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET 0x0000000c 179 #define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB 16 180 #define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB 31 181 #define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK 0xffff0000 182 183 184 185 186 #define TCL_DATA_CMD_DATA_LENGTH_OFFSET 0x00000010 187 #define TCL_DATA_CMD_DATA_LENGTH_LSB 0 188 #define TCL_DATA_CMD_DATA_LENGTH_MSB 15 189 #define TCL_DATA_CMD_DATA_LENGTH_MASK 0x0000ffff 190 191 192 193 194 #define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET 0x00000010 195 #define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB 16 196 #define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB 16 197 #define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK 0x00010000 198 199 200 201 202 #define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 203 #define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 204 #define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB 17 205 #define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 206 207 208 209 210 #define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 211 #define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 212 #define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB 18 213 #define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 214 215 216 217 218 #define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 219 #define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 220 #define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB 19 221 #define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 222 223 224 225 226 #define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 227 #define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 228 #define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB 20 229 #define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 230 231 232 233 234 #define TCL_DATA_CMD_TO_FW_OFFSET 0x00000010 235 #define TCL_DATA_CMD_TO_FW_LSB 21 236 #define TCL_DATA_CMD_TO_FW_MSB 21 237 #define TCL_DATA_CMD_TO_FW_MASK 0x00200000 238 239 240 241 242 #define TCL_DATA_CMD_RESERVED_4A_OFFSET 0x00000010 243 #define TCL_DATA_CMD_RESERVED_4A_LSB 22 244 #define TCL_DATA_CMD_RESERVED_4A_MSB 22 245 #define TCL_DATA_CMD_RESERVED_4A_MASK 0x00400000 246 247 248 249 250 #define TCL_DATA_CMD_PACKET_OFFSET_OFFSET 0x00000010 251 #define TCL_DATA_CMD_PACKET_OFFSET_LSB 23 252 #define TCL_DATA_CMD_PACKET_OFFSET_MSB 31 253 #define TCL_DATA_CMD_PACKET_OFFSET_MASK 0xff800000 254 255 256 257 258 #define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000014 259 #define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB 0 260 #define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB 0 261 #define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK 0x00000001 262 263 264 265 266 #define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000014 267 #define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB 1 268 #define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB 1 269 #define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00000002 270 271 272 273 274 #define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET 0x00000014 275 #define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB 2 276 #define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB 3 277 #define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK 0x0000000c 278 279 280 281 282 #define TCL_DATA_CMD_HLOS_TID_OFFSET 0x00000014 283 #define TCL_DATA_CMD_HLOS_TID_LSB 4 284 #define TCL_DATA_CMD_HLOS_TID_MSB 7 285 #define TCL_DATA_CMD_HLOS_TID_MASK 0x000000f0 286 287 288 289 290 #define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET 0x00000014 291 #define TCL_DATA_CMD_FLOW_OVERRIDE_LSB 8 292 #define TCL_DATA_CMD_FLOW_OVERRIDE_MSB 8 293 #define TCL_DATA_CMD_FLOW_OVERRIDE_MASK 0x00000100 294 295 296 297 298 #define TCL_DATA_CMD_PMAC_ID_OFFSET 0x00000014 299 #define TCL_DATA_CMD_PMAC_ID_LSB 9 300 #define TCL_DATA_CMD_PMAC_ID_MSB 10 301 #define TCL_DATA_CMD_PMAC_ID_MASK 0x00000600 302 303 304 305 306 #define TCL_DATA_CMD_RESERVED_5A_OFFSET 0x00000014 307 #define TCL_DATA_CMD_RESERVED_5A_LSB 11 308 #define TCL_DATA_CMD_RESERVED_5A_MSB 23 309 #define TCL_DATA_CMD_RESERVED_5A_MASK 0x00fff800 310 311 312 313 314 #define TCL_DATA_CMD_VDEV_ID_OFFSET 0x00000014 315 #define TCL_DATA_CMD_VDEV_ID_LSB 24 316 #define TCL_DATA_CMD_VDEV_ID_MSB 31 317 #define TCL_DATA_CMD_VDEV_ID_MASK 0xff000000 318 319 320 321 322 #define TCL_DATA_CMD_SEARCH_INDEX_OFFSET 0x00000018 323 #define TCL_DATA_CMD_SEARCH_INDEX_LSB 0 324 #define TCL_DATA_CMD_SEARCH_INDEX_MSB 19 325 #define TCL_DATA_CMD_SEARCH_INDEX_MASK 0x000fffff 326 327 328 329 330 #define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET 0x00000018 331 #define TCL_DATA_CMD_CACHE_SET_NUM_LSB 20 332 #define TCL_DATA_CMD_CACHE_SET_NUM_MSB 23 333 #define TCL_DATA_CMD_CACHE_SET_NUM_MASK 0x00f00000 334 335 336 337 338 #define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET 0x00000018 339 #define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB 24 340 #define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB 24 341 #define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK 0x01000000 342 343 344 345 346 #define TCL_DATA_CMD_RESERVED_6A_OFFSET 0x00000018 347 #define TCL_DATA_CMD_RESERVED_6A_LSB 25 348 #define TCL_DATA_CMD_RESERVED_6A_MSB 31 349 #define TCL_DATA_CMD_RESERVED_6A_MASK 0xfe000000 350 351 352 353 354 #define TCL_DATA_CMD_RESERVED_7A_OFFSET 0x0000001c 355 #define TCL_DATA_CMD_RESERVED_7A_LSB 0 356 #define TCL_DATA_CMD_RESERVED_7A_MSB 19 357 #define TCL_DATA_CMD_RESERVED_7A_MASK 0x000fffff 358 359 360 361 362 #define TCL_DATA_CMD_RING_ID_OFFSET 0x0000001c 363 #define TCL_DATA_CMD_RING_ID_LSB 20 364 #define TCL_DATA_CMD_RING_ID_MSB 27 365 #define TCL_DATA_CMD_RING_ID_MASK 0x0ff00000 366 367 368 369 370 #define TCL_DATA_CMD_LOOPING_COUNT_OFFSET 0x0000001c 371 #define TCL_DATA_CMD_LOOPING_COUNT_LSB 28 372 #define TCL_DATA_CMD_LOOPING_COUNT_MSB 31 373 #define TCL_DATA_CMD_LOOPING_COUNT_MASK 0xf0000000 374 375 376 377 #endif 378