1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _TCL_GSE_CMD_H_ 31 #define _TCL_GSE_CMD_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #define NUM_OF_DWORDS_TCL_GSE_CMD 8 36 37 38 struct tcl_gse_cmd { 39 uint32_t control_buffer_addr_31_0 : 32; 40 uint32_t control_buffer_addr_39_32 : 8, 41 gse_ctrl : 4, 42 gse_sel : 1, 43 status_destination_ring_id : 1, 44 swap : 1, 45 index_search_en : 1, 46 cache_set_num : 4, 47 reserved_1a : 12; 48 uint32_t tcl_cmd_type : 1, 49 reserved_2a : 31; 50 uint32_t cmd_meta_data_31_0 : 32; 51 uint32_t cmd_meta_data_63_32 : 32; 52 uint32_t reserved_5a : 32; 53 uint32_t reserved_6a : 32; 54 uint32_t reserved_7a : 20, 55 ring_id : 8, 56 looping_count : 4; 57 }; 58 59 60 61 62 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 63 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0 64 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31 65 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff 66 67 68 69 70 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 71 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0 72 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7 73 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff 74 75 76 77 78 #define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004 79 #define TCL_GSE_CMD_GSE_CTRL_LSB 8 80 #define TCL_GSE_CMD_GSE_CTRL_MSB 11 81 #define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00 82 83 84 85 86 #define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004 87 #define TCL_GSE_CMD_GSE_SEL_LSB 12 88 #define TCL_GSE_CMD_GSE_SEL_MSB 12 89 #define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000 90 91 92 93 94 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 95 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13 96 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13 97 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000 98 99 100 101 102 #define TCL_GSE_CMD_SWAP_OFFSET 0x00000004 103 #define TCL_GSE_CMD_SWAP_LSB 14 104 #define TCL_GSE_CMD_SWAP_MSB 14 105 #define TCL_GSE_CMD_SWAP_MASK 0x00004000 106 107 108 109 110 #define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004 111 #define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15 112 #define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15 113 #define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000 114 115 116 117 118 #define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004 119 #define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16 120 #define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19 121 #define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000 122 123 124 125 126 #define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004 127 #define TCL_GSE_CMD_RESERVED_1A_LSB 20 128 #define TCL_GSE_CMD_RESERVED_1A_MSB 31 129 #define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000 130 131 132 133 134 #define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 135 #define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0 136 #define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0 137 #define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001 138 139 140 141 142 #define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008 143 #define TCL_GSE_CMD_RESERVED_2A_LSB 1 144 #define TCL_GSE_CMD_RESERVED_2A_MSB 31 145 #define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe 146 147 148 149 150 #define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c 151 #define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0 152 #define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31 153 #define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff 154 155 156 157 158 #define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010 159 #define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0 160 #define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31 161 #define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff 162 163 164 165 166 #define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014 167 #define TCL_GSE_CMD_RESERVED_5A_LSB 0 168 #define TCL_GSE_CMD_RESERVED_5A_MSB 31 169 #define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff 170 171 172 173 174 #define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018 175 #define TCL_GSE_CMD_RESERVED_6A_LSB 0 176 #define TCL_GSE_CMD_RESERVED_6A_MSB 31 177 #define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff 178 179 180 181 182 #define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c 183 #define TCL_GSE_CMD_RESERVED_7A_LSB 0 184 #define TCL_GSE_CMD_RESERVED_7A_MSB 19 185 #define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff 186 187 188 189 190 #define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c 191 #define TCL_GSE_CMD_RING_ID_LSB 20 192 #define TCL_GSE_CMD_RING_ID_MSB 27 193 #define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000 194 195 196 197 198 #define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c 199 #define TCL_GSE_CMD_LOOPING_COUNT_LSB 28 200 #define TCL_GSE_CMD_LOOPING_COUNT_MSB 31 201 #define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000 202 203 204 205 #endif 206