1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _WBM_RELEASE_RING_RX_H_ 31 #define _WBM_RELEASE_RING_RX_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #include "rx_msdu_desc_info.h" 36 #include "rx_mpdu_desc_info.h" 37 #include "buffer_addr_info.h" 38 #define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 8 39 40 41 struct wbm_release_ring_rx { 42 struct buffer_addr_info released_buff_or_desc_addr_info; 43 uint32_t release_source_module : 3, 44 bm_action : 3, 45 buffer_or_desc_type : 3, 46 first_msdu_index : 4, 47 reserved_2a : 4, 48 rxdma_push_reason : 2, 49 rxdma_error_code : 5, 50 reo_push_reason : 2, 51 reo_error_code : 5, 52 wbm_internal_error : 1; 53 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 54 struct rx_msdu_desc_info rx_msdu_desc_info_details; 55 uint32_t reserved_6a : 32; 56 uint32_t reserved_7a : 20, 57 ring_id : 8, 58 looping_count : 4; 59 }; 60 61 62 63 64 65 66 67 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 68 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 69 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 70 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 71 72 73 74 75 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 76 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 77 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 78 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 79 80 81 82 83 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 84 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 85 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 86 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 87 88 89 90 91 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 92 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 93 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 94 #define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 95 96 97 98 99 #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 100 #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 101 #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 102 #define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 103 104 105 106 107 #define WBM_RELEASE_RING_RX_BM_ACTION_OFFSET 0x00000008 108 #define WBM_RELEASE_RING_RX_BM_ACTION_LSB 3 109 #define WBM_RELEASE_RING_RX_BM_ACTION_MSB 5 110 #define WBM_RELEASE_RING_RX_BM_ACTION_MASK 0x00000038 111 112 113 114 115 #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 116 #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 117 #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 118 #define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 119 120 121 122 123 #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_OFFSET 0x00000008 124 #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_LSB 9 125 #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MSB 12 126 #define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MASK 0x00001e00 127 128 129 130 131 #define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008 132 #define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 13 133 #define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 16 134 #define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x0001e000 135 136 137 138 139 #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 140 #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_LSB 17 141 #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MSB 18 142 #define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 143 144 145 146 147 #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 148 #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_LSB 19 149 #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MSB 23 150 #define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 151 152 153 154 155 #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 156 #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_LSB 24 157 #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MSB 25 158 #define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MASK 0x03000000 159 160 161 162 163 #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 164 #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_LSB 26 165 #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MSB 30 166 #define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 167 168 169 170 171 #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 172 #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_LSB 31 173 #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MSB 31 174 #define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 175 176 177 178 179 180 181 182 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c 183 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 184 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 185 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 186 187 188 189 190 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c 191 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 192 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 193 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 194 195 196 197 198 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c 199 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 200 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 201 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 202 203 204 205 206 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c 207 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 208 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 209 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 210 211 212 213 214 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c 215 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 216 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 217 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 218 219 220 221 222 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c 223 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 224 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 225 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 226 227 228 229 230 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c 231 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 232 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 233 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 234 235 236 237 238 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c 239 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 240 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 241 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 242 243 244 245 246 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_OFFSET 0x0000000c 247 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_LSB 15 248 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_MSB 22 249 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_VDEV_ID_MASK 0x007f8000 250 251 252 253 254 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c 255 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 23 256 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 26 257 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x07800000 258 259 260 261 262 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c 263 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 264 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 265 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 266 267 268 269 270 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c 271 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 272 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 273 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 274 275 276 277 278 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 279 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 280 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 281 #define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 282 283 284 285 286 287 288 289 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 290 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 291 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 292 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 293 294 295 296 297 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 298 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 299 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 300 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 301 302 303 304 305 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 306 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 307 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 308 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 309 310 311 312 313 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 314 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 315 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 316 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 317 318 319 320 321 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 322 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 323 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 324 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 325 326 327 328 329 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 330 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 331 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 332 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 333 334 335 336 337 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 338 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 339 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 340 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 341 342 343 344 345 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 346 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 347 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 348 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 349 350 351 352 353 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 354 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 355 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 356 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 357 358 359 360 361 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 362 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 363 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 364 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 365 366 367 368 369 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 370 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 371 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 372 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 373 374 375 376 377 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 378 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 379 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 380 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 381 382 383 384 385 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 386 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 387 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 388 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 389 390 391 392 393 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 394 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 395 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 396 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 397 398 399 400 401 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 402 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 403 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 404 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 405 406 407 408 409 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000014 410 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 29 411 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 412 #define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xe0000000 413 414 415 416 417 #define WBM_RELEASE_RING_RX_RESERVED_6A_OFFSET 0x00000018 418 #define WBM_RELEASE_RING_RX_RESERVED_6A_LSB 0 419 #define WBM_RELEASE_RING_RX_RESERVED_6A_MSB 31 420 #define WBM_RELEASE_RING_RX_RESERVED_6A_MASK 0xffffffff 421 422 423 424 425 #define WBM_RELEASE_RING_RX_RESERVED_7A_OFFSET 0x0000001c 426 #define WBM_RELEASE_RING_RX_RESERVED_7A_LSB 0 427 #define WBM_RELEASE_RING_RX_RESERVED_7A_MSB 19 428 #define WBM_RELEASE_RING_RX_RESERVED_7A_MASK 0x000fffff 429 430 431 432 433 #define WBM_RELEASE_RING_RX_RING_ID_OFFSET 0x0000001c 434 #define WBM_RELEASE_RING_RX_RING_ID_LSB 20 435 #define WBM_RELEASE_RING_RX_RING_ID_MSB 27 436 #define WBM_RELEASE_RING_RX_RING_ID_MASK 0x0ff00000 437 438 439 440 441 #define WBM_RELEASE_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c 442 #define WBM_RELEASE_RING_RX_LOOPING_COUNT_LSB 28 443 #define WBM_RELEASE_RING_RX_LOOPING_COUNT_MSB 31 444 #define WBM_RELEASE_RING_RX_LOOPING_COUNT_MASK 0xf0000000 445 446 447 448 #endif 449