1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 23 24 25 26 27 28 29 30 #ifndef _WBM_RELEASE_RING_TX_H_ 31 #define _WBM_RELEASE_RING_TX_H_ 32 #if !defined(__ASSEMBLER__) 33 #endif 34 35 #include "tx_rate_stats_info.h" 36 #include "buffer_addr_info.h" 37 #define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 8 38 39 40 struct wbm_release_ring_tx { 41 struct buffer_addr_info released_buff_or_desc_addr_info; 42 uint32_t release_source_module : 3, 43 bm_action : 3, 44 buffer_or_desc_type : 3, 45 first_msdu_index : 4, 46 tqm_release_reason : 4, 47 rbm_override_valid : 1, 48 rbm_override : 4, 49 reserved_2a : 9, 50 wbm_internal_error : 1; 51 uint32_t tqm_status_number : 24, 52 transmit_count : 7, 53 sw_release_details_valid : 1; 54 uint32_t ack_frame_rssi : 8, 55 first_msdu : 1, 56 last_msdu : 1, 57 fw_tx_notify_frame : 3, 58 buffer_timestamp : 19; 59 struct tx_rate_stats_info tx_rate_stats; 60 uint32_t sw_peer_id : 16, 61 tid : 4, 62 ring_id : 8, 63 looping_count : 4; 64 }; 65 66 67 68 69 70 71 72 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 73 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 74 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 75 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 76 77 78 79 80 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 81 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 82 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 83 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 84 85 86 87 88 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 89 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 90 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 91 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 92 93 94 95 96 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 97 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 98 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 99 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 100 101 102 103 104 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 105 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 106 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 107 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 108 109 110 111 112 #define WBM_RELEASE_RING_TX_BM_ACTION_OFFSET 0x00000008 113 #define WBM_RELEASE_RING_TX_BM_ACTION_LSB 3 114 #define WBM_RELEASE_RING_TX_BM_ACTION_MSB 5 115 #define WBM_RELEASE_RING_TX_BM_ACTION_MASK 0x00000038 116 117 118 119 120 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 121 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 122 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 123 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 124 125 126 127 128 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_OFFSET 0x00000008 129 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_LSB 9 130 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MSB 12 131 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MASK 0x00001e00 132 133 134 135 136 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 137 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_LSB 13 138 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MSB 16 139 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 140 141 142 143 144 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 145 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_LSB 17 146 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MSB 17 147 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 148 149 150 151 152 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_OFFSET 0x00000008 153 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_LSB 18 154 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MSB 21 155 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MASK 0x003c0000 156 157 158 159 160 #define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 161 #define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 22 162 #define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 30 163 #define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0x7fc00000 164 165 166 167 168 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 169 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_LSB 31 170 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MSB 31 171 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 172 173 174 175 176 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c 177 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 178 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 23 179 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff 180 181 182 183 184 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c 185 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_LSB 24 186 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MSB 30 187 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 188 189 190 191 192 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c 193 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 194 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 195 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 196 197 198 199 200 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 201 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_LSB 0 202 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MSB 7 203 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff 204 205 206 207 208 #define WBM_RELEASE_RING_TX_FIRST_MSDU_OFFSET 0x00000010 209 #define WBM_RELEASE_RING_TX_FIRST_MSDU_LSB 8 210 #define WBM_RELEASE_RING_TX_FIRST_MSDU_MSB 8 211 #define WBM_RELEASE_RING_TX_FIRST_MSDU_MASK 0x00000100 212 213 214 215 216 #define WBM_RELEASE_RING_TX_LAST_MSDU_OFFSET 0x00000010 217 #define WBM_RELEASE_RING_TX_LAST_MSDU_LSB 9 218 #define WBM_RELEASE_RING_TX_LAST_MSDU_MSB 9 219 #define WBM_RELEASE_RING_TX_LAST_MSDU_MASK 0x00000200 220 221 222 223 224 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 225 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 226 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 227 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 228 229 230 231 232 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 233 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_LSB 13 234 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MSB 31 235 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 236 237 238 239 240 241 242 243 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 244 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 245 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 246 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 247 248 249 250 251 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 252 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 253 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 254 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e 255 256 257 258 259 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 260 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 261 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 262 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 263 264 265 266 267 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 268 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 269 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 270 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 271 272 273 274 275 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 276 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 277 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 278 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 279 280 281 282 283 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 284 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 285 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 286 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 287 288 289 290 291 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 292 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 293 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 294 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 295 296 297 298 299 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 300 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 301 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 302 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 303 304 305 306 307 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 308 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 309 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 310 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 311 312 313 314 315 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 316 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_LSB 29 317 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_MSB 31 318 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_MASK 0xe0000000 319 320 321 322 323 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 324 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 325 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 326 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff 327 328 329 330 331 #define WBM_RELEASE_RING_TX_SW_PEER_ID_OFFSET 0x0000001c 332 #define WBM_RELEASE_RING_TX_SW_PEER_ID_LSB 0 333 #define WBM_RELEASE_RING_TX_SW_PEER_ID_MSB 15 334 #define WBM_RELEASE_RING_TX_SW_PEER_ID_MASK 0x0000ffff 335 336 337 338 339 #define WBM_RELEASE_RING_TX_TID_OFFSET 0x0000001c 340 #define WBM_RELEASE_RING_TX_TID_LSB 16 341 #define WBM_RELEASE_RING_TX_TID_MSB 19 342 #define WBM_RELEASE_RING_TX_TID_MASK 0x000f0000 343 344 345 346 347 #define WBM_RELEASE_RING_TX_RING_ID_OFFSET 0x0000001c 348 #define WBM_RELEASE_RING_TX_RING_ID_LSB 20 349 #define WBM_RELEASE_RING_TX_RING_ID_MSB 27 350 #define WBM_RELEASE_RING_TX_RING_ID_MASK 0x0ff00000 351 352 353 354 355 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c 356 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_LSB 28 357 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_MSB 31 358 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_MASK 0xf0000000 359 360 361 362 #endif 363