1 2 /* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 #ifndef __WCSS_SEQ_HWIOREG_UMAC_H__ 22 #define __WCSS_SEQ_HWIOREG_UMAC_H__ 23 24 25 26 27 #include "seq_hwio.h" 28 #include "wcss_seq_hwiobase.h" 29 #ifdef SCALE_INCLUDES 30 #include "HALhwio.h" 31 #else 32 #include "msmhwio.h" 33 #endif 34 35 #define REO_REG_REG_BASE (UMAC_BASE + 0x00038000) 36 #define REO_REG_REG_BASE_SIZE 0x4000 37 #define REO_REG_REG_BASE_USED 0x309c 38 #define REO_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00038000) 39 #define REO_REG_REG_BASE_OFFS 0x00038000 40 #define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000) 41 #define WBM_REG_REG_BASE (UMAC_BASE + 0x00034000) 42 #define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff 43 44 #define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x7fc 45 #define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 2 46 47 #define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x2 48 #define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 1 49 50 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x800000 51 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23 52 #define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 53 #define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 16 54 #define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0xffff 55 #define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0 56 57 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 58 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 59 60 #define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) ((x) + 0xc4) 61 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 62 63 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 64 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 65 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) ((x) + 0xd0) 66 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base, n) ((base) + 0X88 + (0x4*(n))) 67 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_PHYS(base, n) ((base) + 0X88 + (0x4*(n))) 68 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_OFFS(n) (0X88 + (0x4*(n))) 69 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_RMSK 0x7ffff 70 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_MAXn 7 71 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_POR 0x00000038 72 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_POR_RMSK 0xffffffff 73 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_ATTR 0x3 74 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_INI(base, n) \ 75 in_dword_masked(HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base, n), HWIO_TCL_R0_SW_CONFIG_BANK_n_RMSK) 76 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_INMI(base, n, mask) \ 77 in_dword_masked(HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base, n), mask) 78 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_OUTI(base, n, val) \ 79 out_dword(HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base, n), val) 80 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_OUTMI(base, n, mask, val) \ 81 out_dword_masked_ns(HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base, n), mask, val, HWIO_TCL_R0_SW_CONFIG_BANK_n_INI(base, n)) 82 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_BMSK 0x60000 83 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT 17 84 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_BMSK 0x18000 85 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT 15 86 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_BMSK 0x4000 87 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT 14 88 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_BMSK 0x3000 89 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT 12 90 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_BMSK 0x800 91 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT 11 92 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_BMSK 0x400 93 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT 10 94 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_BMSK 0x200 95 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT 9 96 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_BMSK 0x100 97 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT 8 98 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_BMSK 0x80 99 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT 7 100 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_BMSK 0x78 101 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT 3 102 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_BMSK 0x6 103 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT 1 104 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_BMSK 0x1 105 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT 0 106 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23 107 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 108 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 8 109 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0xff 110 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0 111 112 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) ((x) + 0xe0) 113 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) ((x) + 0xd4) 114 115 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff 116 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 117 118 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 119 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 120 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff 121 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 122 123 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) ((x) + 0xf0) 124 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 125 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 126 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff 127 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 128 129 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x1fff00 130 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 8 131 132 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 133 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 134 135 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 136 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 137 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) ((x) + 0xfc) 138 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff 139 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 140 141 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) ((x) + 0xf0) 142 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) ((x) + 0xf4) 143 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x1fff00 144 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 8 145 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 8 146 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) ((x) + 0xe4) 147 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff 148 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 149 150 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) ((x) + 0xb6c) 151 152 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 153 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 154 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0xf0000000 155 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 28 156 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_BMSK 0xf000000 157 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 24 158 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_BMSK 0xf00000 159 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 20 160 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_BMSK 0xf0000 161 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 16 162 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_BMSK 0xf000 163 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 12 164 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_BMSK 0xf00 165 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 8 166 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_BMSK 0xf0 167 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 4 168 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_BMSK 0xf 169 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0 170 171 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0xf0000000 172 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 28 173 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_BMSK 0xf000000 174 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 24 175 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_BMSK 0xf00000 176 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 20 177 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_BMSK 0xf0000 178 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 16 179 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_BMSK 0xf000 180 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 12 181 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_BMSK 0xf00 182 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 8 183 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_BMSK 0xf0 184 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 4 185 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_BMSK 0xf 186 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0 187 188 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 189 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 190 191 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 192 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 193 194 #define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK 0x100000 195 #define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT 20 196 #define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK 0x80000 197 #define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT 19 198 #define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 199 #define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 200 #define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 201 #define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 202 #define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 203 #define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 204 #define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff 205 #define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 206 #define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 207 #define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 208 #define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 209 #define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 210 #define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff 211 #define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 212 #define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 213 #define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 214 215 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_BMSK 0x100 216 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_SHFT 8 217 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_BMSK 0x80 218 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_SHFT 7 219 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_BMSK 0x40 220 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_SHFT 6 221 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_BMSK 0x20 222 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_SHFT 5 223 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_BMSK 0x10 224 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_SHFT 4 225 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_BMSK 0x8 226 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_SHFT 3 227 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_BMSK 0x4 228 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_SHFT 2 229 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_BMSK 0x2 230 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_SHFT 1 231 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_BMSK 0x1 232 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_SHFT 0 233 234 235 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0x878) 236 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x3f0) 237 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x3bc) 238 #define HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x34) 239 #define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x) ((x) + 0x74) 240 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x3f4) 241 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) ((x) + 0x3a8) 242 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x3c8) 243 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) ((x) + 0x888) 244 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x894) 245 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x898) 246 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x8c0) 247 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x8c4) 248 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0x8c8) 249 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0x87c) 250 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x8a8) 251 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x8ac) 252 253 #define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) ((x) + 0x2000) 254 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) ((x) + 0x880) 255 #define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) ((x) + 0x2004) 256 #define HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x38) 257 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x3b8) 258 #define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x3ac) 259 260 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) ((x) + 0x3a4) 261 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x3ec) 262 263 #define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x3b4) 264 #define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) ((x) + 0x303c) 265 #define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) ((x) + 0x3038) 266 #define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x54) 267 #define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x50) 268 #define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) ((x) + 0x60) 269 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 270 #define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) ((x) + 0xe0) 271 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 272 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 273 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 274 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 275 #define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) ((x) + 0xc0) 276 #define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n) ((base) + 0X1F8 + (0x4*(n))) 277 #define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0) 278 #define HWIO_REO_R0_GENERAL_ENABLE_PHYS(x) ((x) + 0x0) 279 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) ((x) + 0x994) 280 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) ((x) + 0x998) 281 #define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base, n) ((base) + 0X88 + (0x4*(n))) 282 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) ((x) + 0x99c) 283 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) ((x) + 0x9a0) 284 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) 285 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) ((x) + 0x20) 286 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) 287 #define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) ((x) + 0x678) 288 #define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) ((x) + 0x6a0) 289 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x8 290 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 2 291 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x4 292 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 3 293 #define HWIO_REO_R0_MISC_CTL_ADDR(x) ((x) + 0xa08) 294 #define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK 0x1e00000 295 #define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT 21 296 #define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x1e0000 297 #define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 17 298 299 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0xf0000000 300 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 28 301 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0xf000000 302 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 24 303 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0xf00000 304 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 20 305 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0xf0000 306 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 16 307 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0xf000 308 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 12 309 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0xf00 310 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 8 311 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0xf0 312 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 4 313 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0xf 314 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0 315 316 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 24 317 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_BMSK 0xf00000 318 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 20 319 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_BMSK 0xf0000 320 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 16 321 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_BMSK 0xf000 322 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 12 323 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_BMSK 0xf00 324 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 8 325 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_BMSK 0xf0 326 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 4 327 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_BMSK 0xf 328 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0 329 330 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0xf0000000 331 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 28 332 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_BMSK 0xf000000 333 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 24 334 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_BMSK 0xf00000 335 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 20 336 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_BMSK 0xf0000 337 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 16 338 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_BMSK 0xf000 339 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 12 340 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_BMSK 0xf00 341 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 8 342 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_BMSK 0xf0 343 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 4 344 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_BMSK 0xf 345 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0 346 347 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 348 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8 349 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 350 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 351 #define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 352 #define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT 8 353 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x1d4) 354 #define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) ((x) + 0x3018) 355 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 356 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8 357 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) ((x) + 0x160) 358 #define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) ((x) + 0x3010) 359 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 360 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 8 361 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x914) 362 #define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) ((x) + 0x3098) 363 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 364 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 365 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) ((x) + 0x8ec) 366 #define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) ((x) + 0x2008) 367 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x) ((x) + 0xabc) 368 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x) ((x) + 0x2028) 369 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 370 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT 8 371 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) ((x) + 0xc8c) 372 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) ((x) + 0x2048) 373 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 374 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 8 375 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xb5c) 376 #define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) ((x) + 0x30b8) 377 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 378 #define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 379 #define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x268) 380 #define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3018) 381 #define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 382 #define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 383 #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xc20) 384 #define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x) ((x) + 0x30c8) 385 #define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xc94) 386 #define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x30d0) 387 #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 388 #define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 389 #define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x3fc) 390 #define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x400) 391 #define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x404) 392 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x3f8) 393 394 #define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0x744) 395 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x418) 396 #define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x) ((x) + 0x3078) 397 #define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) ((x) + 0x3040) 398 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) ((x) + 0x28) 399 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) ((x) + 0x2c) 400 #define HWIO_REO_R0_PN_IN_DEST_ADDR(x) ((x) + 0x4c) 401 #define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0xffffff 402 #define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0xef 403 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK 0xe00000 404 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 21 405 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK 0x1c0000 406 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 18 407 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK 0x38000 408 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 15 409 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK 0x7000 410 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 12 411 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK 0xe00 412 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 9 413 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK 0x1c0 414 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 6 415 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK 0x38 416 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 3 417 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK 0x7 418 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT 0 419 420 #define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000) 421 #define MAC_TCL_REG_REG_BASE_SIZE 0x3000 422 #define MAC_TCL_REG_REG_BASE_USED 0x205c 423 #define MAC_TCL_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00044000) 424 #define MAC_TCL_REG_REG_BASE_OFFS 0x00044000 425 426 427 #endif 428