1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _COEX_TX_STATUS_H_ 21 #define _COEX_TX_STATUS_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #define NUM_OF_DWORDS_COEX_TX_STATUS 4 26 27 #define NUM_OF_QWORDS_COEX_TX_STATUS 2 28 29 struct coex_tx_status { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t reserved_0a : 7, 32 tx_bw : 3, 33 tx_status_reason : 3, 34 tx_wait_ack : 1, 35 fes_tx_is_gen_frame : 1, 36 sch_tx_burst_ongoing : 1, 37 current_tx_duration : 16; 38 uint32_t next_rx_active_time : 16, 39 remaining_fes_time : 16; 40 uint32_t tx_antenna_mask : 8, 41 shared_ant_tx_pwr : 8, 42 other_ant_tx_pwr : 8, 43 reserved_2 : 8; 44 uint32_t tlv64_padding : 32; 45 #else 46 uint32_t current_tx_duration : 16, 47 sch_tx_burst_ongoing : 1, 48 fes_tx_is_gen_frame : 1, 49 tx_wait_ack : 1, 50 tx_status_reason : 3, 51 tx_bw : 3, 52 reserved_0a : 7; 53 uint32_t remaining_fes_time : 16, 54 next_rx_active_time : 16; 55 uint32_t reserved_2 : 8, 56 other_ant_tx_pwr : 8, 57 shared_ant_tx_pwr : 8, 58 tx_antenna_mask : 8; 59 uint32_t tlv64_padding : 32; 60 #endif 61 }; 62 63 #define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000 64 #define COEX_TX_STATUS_RESERVED_0A_LSB 0 65 #define COEX_TX_STATUS_RESERVED_0A_MSB 6 66 #define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f 67 68 #define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000 69 #define COEX_TX_STATUS_TX_BW_LSB 7 70 #define COEX_TX_STATUS_TX_BW_MSB 9 71 #define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380 72 73 #define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000 74 #define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 75 #define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 76 #define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00 77 78 #define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000 79 #define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 80 #define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 81 #define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000 82 83 #define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000 84 #define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 85 #define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 86 #define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000 87 88 #define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000 89 #define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 90 #define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 91 #define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000 92 93 #define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000 94 #define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 95 #define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 96 #define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000 97 98 #define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000 99 #define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32 100 #define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47 101 #define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000 102 103 #define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000 104 #define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48 105 #define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63 106 #define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000 107 108 #define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008 109 #define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 110 #define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 111 #define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff 112 113 #define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008 114 #define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 115 #define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 116 #define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00 117 118 #define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008 119 #define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 120 #define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 121 #define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000 122 123 #define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008 124 #define COEX_TX_STATUS_RESERVED_2_LSB 24 125 #define COEX_TX_STATUS_RESERVED_2_MSB 31 126 #define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000 127 128 #define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008 129 #define COEX_TX_STATUS_TLV64_PADDING_LSB 32 130 #define COEX_TX_STATUS_TLV64_PADDING_MSB 63 131 #define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 132 133 #endif 134