1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _EXPECTED_RESPONSE_H_ 21 #define _EXPECTED_RESPONSE_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #define NUM_OF_DWORDS_EXPECTED_RESPONSE 6 26 27 #define NUM_OF_QWORDS_EXPECTED_RESPONSE 3 28 29 struct expected_response { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t tx_ad2_31_0 : 32; 32 uint32_t tx_ad2_47_32 : 16, 33 expected_response_type : 5, 34 response_to_response : 3, 35 su_ba_user_number : 1, 36 response_info_part2_required : 1, 37 transmitted_bssid_check_en : 1, 38 reserved_1 : 5; 39 uint32_t ndp_sta_partial_aid_2_8_0 : 11, 40 reserved_2 : 10, 41 ndp_sta_partial_aid1_8_0 : 11; 42 uint32_t ast_index : 16, 43 capture_ack_ba_sounding : 1, 44 capture_sounding_1str_20mhz : 1, 45 capture_sounding_1str_40mhz : 1, 46 capture_sounding_1str_80mhz : 1, 47 capture_sounding_1str_160mhz : 1, 48 capture_sounding_1str_240mhz : 1, 49 capture_sounding_1str_320mhz : 1, 50 reserved_3a : 9; 51 uint32_t fcs : 9, 52 reserved_4a : 1, 53 crc : 4, 54 scrambler_seed : 7, 55 reserved_4b : 11; 56 uint32_t tlv64_padding : 32; 57 #else 58 uint32_t tx_ad2_31_0 : 32; 59 uint32_t reserved_1 : 5, 60 transmitted_bssid_check_en : 1, 61 response_info_part2_required : 1, 62 su_ba_user_number : 1, 63 response_to_response : 3, 64 expected_response_type : 5, 65 tx_ad2_47_32 : 16; 66 uint32_t ndp_sta_partial_aid1_8_0 : 11, 67 reserved_2 : 10, 68 ndp_sta_partial_aid_2_8_0 : 11; 69 uint32_t reserved_3a : 9, 70 capture_sounding_1str_320mhz : 1, 71 capture_sounding_1str_240mhz : 1, 72 capture_sounding_1str_160mhz : 1, 73 capture_sounding_1str_80mhz : 1, 74 capture_sounding_1str_40mhz : 1, 75 capture_sounding_1str_20mhz : 1, 76 capture_ack_ba_sounding : 1, 77 ast_index : 16; 78 uint32_t reserved_4b : 11, 79 scrambler_seed : 7, 80 crc : 4, 81 reserved_4a : 1, 82 fcs : 9; 83 uint32_t tlv64_padding : 32; 84 #endif 85 }; 86 87 #define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000 88 #define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 89 #define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 90 #define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff 91 92 #define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000 93 #define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32 94 #define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47 95 #define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000 96 97 #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000 98 #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48 99 #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52 100 #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000 101 102 #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 103 #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53 104 #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55 105 #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000 106 107 #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000 108 #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56 109 #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56 110 #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000 111 112 #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 113 #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57 114 #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57 115 #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000 116 117 #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 118 #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58 119 #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58 120 #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000 121 122 #define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000 123 #define EXPECTED_RESPONSE_RESERVED_1_LSB 59 124 #define EXPECTED_RESPONSE_RESERVED_1_MSB 63 125 #define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf800000000000000 126 127 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008 128 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 129 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 130 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff 131 132 #define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008 133 #define EXPECTED_RESPONSE_RESERVED_2_LSB 11 134 #define EXPECTED_RESPONSE_RESERVED_2_MSB 20 135 #define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800 136 137 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008 138 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 139 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 140 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000 141 142 #define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008 143 #define EXPECTED_RESPONSE_AST_INDEX_LSB 32 144 #define EXPECTED_RESPONSE_AST_INDEX_MSB 47 145 #define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000 146 147 #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008 148 #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48 149 #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48 150 #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000 151 152 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008 153 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49 154 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49 155 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000 156 157 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008 158 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50 159 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50 160 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000 161 162 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008 163 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51 164 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51 165 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000 166 167 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008 168 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52 169 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52 170 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000 171 172 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008 173 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53 174 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53 175 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000 176 177 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008 178 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54 179 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54 180 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000 181 182 #define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008 183 #define EXPECTED_RESPONSE_RESERVED_3A_LSB 55 184 #define EXPECTED_RESPONSE_RESERVED_3A_MSB 63 185 #define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000 186 187 #define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010 188 #define EXPECTED_RESPONSE_FCS_LSB 0 189 #define EXPECTED_RESPONSE_FCS_MSB 8 190 #define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff 191 192 #define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x0000000000000010 193 #define EXPECTED_RESPONSE_RESERVED_4A_LSB 9 194 #define EXPECTED_RESPONSE_RESERVED_4A_MSB 9 195 #define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x0000000000000200 196 197 #define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010 198 #define EXPECTED_RESPONSE_CRC_LSB 10 199 #define EXPECTED_RESPONSE_CRC_MSB 13 200 #define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00 201 202 #define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010 203 #define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 204 #define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 205 #define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000 206 207 #define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010 208 #define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 209 #define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 210 #define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000 211 212 #define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010 213 #define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32 214 #define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63 215 #define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 216 217 #endif 218