xref: /wlan-driver/fw-api/hw/kiwi/v2/he_sig_b2_mu_info.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /*
3  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 
21 
22 #ifndef _HE_SIG_B2_MU_INFO_H_
23 #define _HE_SIG_B2_MU_INFO_H_
24 #if !defined(__ASSEMBLER__)
25 #endif
26 
27 #define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2
28 
29 struct he_sig_b2_mu_info {
30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
31              uint32_t sta_id                                                  : 11,
32                       sta_spatial_config                                      :  4,
33                       sta_mcs                                                 :  4,
34                       reserved_set_to_1                                       :  1,
35                       sta_coding                                              :  1,
36                       reserved_0a                                             :  7,
37                       nsts                                                    :  3,
38                       rx_integrity_check_passed                               :  1;
39              uint32_t user_order                                              :  8,
40                       cc_mask                                                 :  8,
41                       reserved_1a                                             : 16;
42 #else
43              uint32_t rx_integrity_check_passed                               :  1,
44                       nsts                                                    :  3,
45                       reserved_0a                                             :  7,
46                       sta_coding                                              :  1,
47                       reserved_set_to_1                                       :  1,
48                       sta_mcs                                                 :  4,
49                       sta_spatial_config                                      :  4,
50                       sta_id                                                  : 11;
51              uint32_t reserved_1a                                             : 16,
52                       cc_mask                                                 :  8,
53                       user_order                                              :  8;
54 #endif
55 };
56 
57 #define HE_SIG_B2_MU_INFO_STA_ID_OFFSET                                             0x00000000
58 #define HE_SIG_B2_MU_INFO_STA_ID_LSB                                                0
59 #define HE_SIG_B2_MU_INFO_STA_ID_MSB                                                10
60 #define HE_SIG_B2_MU_INFO_STA_ID_MASK                                               0x000007ff
61 
62 #define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET                                 0x00000000
63 #define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB                                    11
64 #define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB                                    14
65 #define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK                                   0x00007800
66 
67 #define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET                                            0x00000000
68 #define HE_SIG_B2_MU_INFO_STA_MCS_LSB                                               15
69 #define HE_SIG_B2_MU_INFO_STA_MCS_MSB                                               18
70 #define HE_SIG_B2_MU_INFO_STA_MCS_MASK                                              0x00078000
71 
72 #define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET                                  0x00000000
73 #define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB                                     19
74 #define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB                                     19
75 #define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK                                    0x00080000
76 
77 #define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET                                         0x00000000
78 #define HE_SIG_B2_MU_INFO_STA_CODING_LSB                                            20
79 #define HE_SIG_B2_MU_INFO_STA_CODING_MSB                                            20
80 #define HE_SIG_B2_MU_INFO_STA_CODING_MASK                                           0x00100000
81 
82 #define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET                                        0x00000000
83 #define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB                                           21
84 #define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB                                           27
85 #define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK                                          0x0fe00000
86 
87 #define HE_SIG_B2_MU_INFO_NSTS_OFFSET                                               0x00000000
88 #define HE_SIG_B2_MU_INFO_NSTS_LSB                                                  28
89 #define HE_SIG_B2_MU_INFO_NSTS_MSB                                                  30
90 #define HE_SIG_B2_MU_INFO_NSTS_MASK                                                 0x70000000
91 
92 #define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000000
93 #define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
94 #define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
95 #define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
96 
97 #define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET                                         0x00000004
98 #define HE_SIG_B2_MU_INFO_USER_ORDER_LSB                                            0
99 #define HE_SIG_B2_MU_INFO_USER_ORDER_MSB                                            7
100 #define HE_SIG_B2_MU_INFO_USER_ORDER_MASK                                           0x000000ff
101 
102 #define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET                                            0x00000004
103 #define HE_SIG_B2_MU_INFO_CC_MASK_LSB                                               8
104 #define HE_SIG_B2_MU_INFO_CC_MASK_MSB                                               15
105 #define HE_SIG_B2_MU_INFO_CC_MASK_MASK                                              0x0000ff00
106 
107 #define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET                                        0x00000004
108 #define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB                                           16
109 #define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB                                           31
110 #define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK                                          0xffff0000
111 
112 #endif
113