1*5113495bSYour Name 2*5113495bSYour Name /* 3*5113495bSYour Name * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4*5113495bSYour Name * 5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 6*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 7*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 8*5113495bSYour Name * 9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16*5113495bSYour Name */ 17*5113495bSYour Name 18*5113495bSYour Name 19*5113495bSYour Name 20*5113495bSYour Name #ifndef _MACTX_PHY_DESC_H_ 21*5113495bSYour Name #define _MACTX_PHY_DESC_H_ 22*5113495bSYour Name #if !defined(__ASSEMBLER__) 23*5113495bSYour Name #endif 24*5113495bSYour Name 25*5113495bSYour Name #define NUM_OF_DWORDS_MACTX_PHY_DESC 4 26*5113495bSYour Name 27*5113495bSYour Name #define NUM_OF_QWORDS_MACTX_PHY_DESC 2 28*5113495bSYour Name 29*5113495bSYour Name struct mactx_phy_desc { 30*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31*5113495bSYour Name uint32_t reserved_0a : 16, 32*5113495bSYour Name bf_type : 2, 33*5113495bSYour Name wait_sifs : 2, 34*5113495bSYour Name dot11b_preamble_type : 1, 35*5113495bSYour Name pkt_type : 4, 36*5113495bSYour Name su_or_mu : 2, 37*5113495bSYour Name mu_type : 1, 38*5113495bSYour Name bandwidth : 3, 39*5113495bSYour Name channel_capture : 1; 40*5113495bSYour Name uint32_t mcs : 4, 41*5113495bSYour Name global_ofdma_mimo_enable : 1, 42*5113495bSYour Name reserved_1a : 1, 43*5113495bSYour Name stbc : 1, 44*5113495bSYour Name dot11ax_su_extended : 1, 45*5113495bSYour Name dot11ax_trigger_frame_embedded : 1, 46*5113495bSYour Name tx_pwr_shared : 8, 47*5113495bSYour Name tx_pwr_unshared : 8, 48*5113495bSYour Name measure_power : 1, 49*5113495bSYour Name tpc_glut_self_cal : 1, 50*5113495bSYour Name back_to_back_transmission_expected : 1, 51*5113495bSYour Name heavy_clip_nss : 3, 52*5113495bSYour Name txbf_per_packet_no_csd_no_walsh : 1; 53*5113495bSYour Name uint32_t ndp : 2, 54*5113495bSYour Name ul_flag : 1, 55*5113495bSYour Name triggered : 1, 56*5113495bSYour Name ap_pkt_bw : 3, 57*5113495bSYour Name ru_position_start : 8, 58*5113495bSYour Name pcu_ppdu_setup_start_reason : 3, 59*5113495bSYour Name tlv_source : 1, 60*5113495bSYour Name reserved_2a : 2, 61*5113495bSYour Name nss : 3, 62*5113495bSYour Name stream_offset : 3, 63*5113495bSYour Name reserved_2b : 2, 64*5113495bSYour Name clpc_enable : 1, 65*5113495bSYour Name mu_ndp : 1, 66*5113495bSYour Name response_expected : 1; 67*5113495bSYour Name uint32_t rx_chain_mask : 8, 68*5113495bSYour Name rx_chain_mask_valid : 1, 69*5113495bSYour Name ant_sel_valid : 1, 70*5113495bSYour Name ant_sel : 1, 71*5113495bSYour Name cp_setting : 2, 72*5113495bSYour Name he_ppdu_subtype : 2, 73*5113495bSYour Name active_channel : 3, 74*5113495bSYour Name generate_phyrx_tx_start_timing : 1, 75*5113495bSYour Name ltf_size : 2, 76*5113495bSYour Name ru_size_updated_v2 : 4, 77*5113495bSYour Name reserved_3c : 1, 78*5113495bSYour Name u_sig_puncture_pattern_encoding : 6; 79*5113495bSYour Name #else 80*5113495bSYour Name uint32_t channel_capture : 1, 81*5113495bSYour Name bandwidth : 3, 82*5113495bSYour Name mu_type : 1, 83*5113495bSYour Name su_or_mu : 2, 84*5113495bSYour Name pkt_type : 4, 85*5113495bSYour Name dot11b_preamble_type : 1, 86*5113495bSYour Name wait_sifs : 2, 87*5113495bSYour Name bf_type : 2, 88*5113495bSYour Name reserved_0a : 16; 89*5113495bSYour Name uint32_t txbf_per_packet_no_csd_no_walsh : 1, 90*5113495bSYour Name heavy_clip_nss : 3, 91*5113495bSYour Name back_to_back_transmission_expected : 1, 92*5113495bSYour Name tpc_glut_self_cal : 1, 93*5113495bSYour Name measure_power : 1, 94*5113495bSYour Name tx_pwr_unshared : 8, 95*5113495bSYour Name tx_pwr_shared : 8, 96*5113495bSYour Name dot11ax_trigger_frame_embedded : 1, 97*5113495bSYour Name dot11ax_su_extended : 1, 98*5113495bSYour Name stbc : 1, 99*5113495bSYour Name reserved_1a : 1, 100*5113495bSYour Name global_ofdma_mimo_enable : 1, 101*5113495bSYour Name mcs : 4; 102*5113495bSYour Name uint32_t response_expected : 1, 103*5113495bSYour Name mu_ndp : 1, 104*5113495bSYour Name clpc_enable : 1, 105*5113495bSYour Name reserved_2b : 2, 106*5113495bSYour Name stream_offset : 3, 107*5113495bSYour Name nss : 3, 108*5113495bSYour Name reserved_2a : 2, 109*5113495bSYour Name tlv_source : 1, 110*5113495bSYour Name pcu_ppdu_setup_start_reason : 3, 111*5113495bSYour Name ru_position_start : 8, 112*5113495bSYour Name ap_pkt_bw : 3, 113*5113495bSYour Name triggered : 1, 114*5113495bSYour Name ul_flag : 1, 115*5113495bSYour Name ndp : 2; 116*5113495bSYour Name uint32_t u_sig_puncture_pattern_encoding : 6, 117*5113495bSYour Name reserved_3c : 1, 118*5113495bSYour Name ru_size_updated_v2 : 4, 119*5113495bSYour Name ltf_size : 2, 120*5113495bSYour Name generate_phyrx_tx_start_timing : 1, 121*5113495bSYour Name active_channel : 3, 122*5113495bSYour Name he_ppdu_subtype : 2, 123*5113495bSYour Name cp_setting : 2, 124*5113495bSYour Name ant_sel : 1, 125*5113495bSYour Name ant_sel_valid : 1, 126*5113495bSYour Name rx_chain_mask_valid : 1, 127*5113495bSYour Name rx_chain_mask : 8; 128*5113495bSYour Name #endif 129*5113495bSYour Name }; 130*5113495bSYour Name 131*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000 132*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_0A_LSB 0 133*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_0A_MSB 15 134*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff 135*5113495bSYour Name 136*5113495bSYour Name #define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000 137*5113495bSYour Name #define MACTX_PHY_DESC_BF_TYPE_LSB 16 138*5113495bSYour Name #define MACTX_PHY_DESC_BF_TYPE_MSB 17 139*5113495bSYour Name #define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000 140*5113495bSYour Name 141*5113495bSYour Name #define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000 142*5113495bSYour Name #define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 143*5113495bSYour Name #define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 144*5113495bSYour Name #define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000 145*5113495bSYour Name 146*5113495bSYour Name #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000 147*5113495bSYour Name #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 148*5113495bSYour Name #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 149*5113495bSYour Name #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000 150*5113495bSYour Name 151*5113495bSYour Name #define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000 152*5113495bSYour Name #define MACTX_PHY_DESC_PKT_TYPE_LSB 21 153*5113495bSYour Name #define MACTX_PHY_DESC_PKT_TYPE_MSB 24 154*5113495bSYour Name #define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000 155*5113495bSYour Name 156*5113495bSYour Name #define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000 157*5113495bSYour Name #define MACTX_PHY_DESC_SU_OR_MU_LSB 25 158*5113495bSYour Name #define MACTX_PHY_DESC_SU_OR_MU_MSB 26 159*5113495bSYour Name #define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000 160*5113495bSYour Name 161*5113495bSYour Name #define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000 162*5113495bSYour Name #define MACTX_PHY_DESC_MU_TYPE_LSB 27 163*5113495bSYour Name #define MACTX_PHY_DESC_MU_TYPE_MSB 27 164*5113495bSYour Name #define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000 165*5113495bSYour Name 166*5113495bSYour Name #define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000 167*5113495bSYour Name #define MACTX_PHY_DESC_BANDWIDTH_LSB 28 168*5113495bSYour Name #define MACTX_PHY_DESC_BANDWIDTH_MSB 30 169*5113495bSYour Name #define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000 170*5113495bSYour Name 171*5113495bSYour Name #define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000 172*5113495bSYour Name #define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 173*5113495bSYour Name #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 174*5113495bSYour Name #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000 175*5113495bSYour Name 176*5113495bSYour Name #define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000 177*5113495bSYour Name #define MACTX_PHY_DESC_MCS_LSB 32 178*5113495bSYour Name #define MACTX_PHY_DESC_MCS_MSB 35 179*5113495bSYour Name #define MACTX_PHY_DESC_MCS_MASK 0x0000000f00000000 180*5113495bSYour Name 181*5113495bSYour Name #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000 182*5113495bSYour Name #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 36 183*5113495bSYour Name #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 36 184*5113495bSYour Name #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000001000000000 185*5113495bSYour Name 186*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x0000000000000000 187*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_1A_LSB 37 188*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_1A_MSB 37 189*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_1A_MASK 0x0000002000000000 190*5113495bSYour Name 191*5113495bSYour Name #define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000 192*5113495bSYour Name #define MACTX_PHY_DESC_STBC_LSB 38 193*5113495bSYour Name #define MACTX_PHY_DESC_STBC_MSB 38 194*5113495bSYour Name #define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000 195*5113495bSYour Name 196*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 197*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39 198*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39 199*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000 200*5113495bSYour Name 201*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000 202*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40 203*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40 204*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000 205*5113495bSYour Name 206*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000 207*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41 208*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48 209*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000 210*5113495bSYour Name 211*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000 212*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49 213*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56 214*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000 215*5113495bSYour Name 216*5113495bSYour Name #define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000 217*5113495bSYour Name #define MACTX_PHY_DESC_MEASURE_POWER_LSB 57 218*5113495bSYour Name #define MACTX_PHY_DESC_MEASURE_POWER_MSB 57 219*5113495bSYour Name #define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000 220*5113495bSYour Name 221*5113495bSYour Name #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000 222*5113495bSYour Name #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58 223*5113495bSYour Name #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58 224*5113495bSYour Name #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000 225*5113495bSYour Name 226*5113495bSYour Name #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000 227*5113495bSYour Name #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59 228*5113495bSYour Name #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59 229*5113495bSYour Name #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000 230*5113495bSYour Name 231*5113495bSYour Name #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000 232*5113495bSYour Name #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60 233*5113495bSYour Name #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62 234*5113495bSYour Name #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000 235*5113495bSYour Name 236*5113495bSYour Name #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000 237*5113495bSYour Name #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63 238*5113495bSYour Name #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63 239*5113495bSYour Name #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000 240*5113495bSYour Name 241*5113495bSYour Name #define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008 242*5113495bSYour Name #define MACTX_PHY_DESC_NDP_LSB 0 243*5113495bSYour Name #define MACTX_PHY_DESC_NDP_MSB 1 244*5113495bSYour Name #define MACTX_PHY_DESC_NDP_MASK 0x0000000000000003 245*5113495bSYour Name 246*5113495bSYour Name #define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008 247*5113495bSYour Name #define MACTX_PHY_DESC_UL_FLAG_LSB 2 248*5113495bSYour Name #define MACTX_PHY_DESC_UL_FLAG_MSB 2 249*5113495bSYour Name #define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000004 250*5113495bSYour Name 251*5113495bSYour Name #define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008 252*5113495bSYour Name #define MACTX_PHY_DESC_TRIGGERED_LSB 3 253*5113495bSYour Name #define MACTX_PHY_DESC_TRIGGERED_MSB 3 254*5113495bSYour Name #define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000008 255*5113495bSYour Name 256*5113495bSYour Name #define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008 257*5113495bSYour Name #define MACTX_PHY_DESC_AP_PKT_BW_LSB 4 258*5113495bSYour Name #define MACTX_PHY_DESC_AP_PKT_BW_MSB 6 259*5113495bSYour Name #define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x0000000000000070 260*5113495bSYour Name 261*5113495bSYour Name #define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008 262*5113495bSYour Name #define MACTX_PHY_DESC_RU_POSITION_START_LSB 7 263*5113495bSYour Name #define MACTX_PHY_DESC_RU_POSITION_START_MSB 14 264*5113495bSYour Name #define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x0000000000007f80 265*5113495bSYour Name 266*5113495bSYour Name #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008 267*5113495bSYour Name #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15 268*5113495bSYour Name #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17 269*5113495bSYour Name #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000038000 270*5113495bSYour Name 271*5113495bSYour Name #define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008 272*5113495bSYour Name #define MACTX_PHY_DESC_TLV_SOURCE_LSB 18 273*5113495bSYour Name #define MACTX_PHY_DESC_TLV_SOURCE_MSB 18 274*5113495bSYour Name #define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000040000 275*5113495bSYour Name 276*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008 277*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2A_LSB 19 278*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2A_MSB 20 279*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000180000 280*5113495bSYour Name 281*5113495bSYour Name #define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008 282*5113495bSYour Name #define MACTX_PHY_DESC_NSS_LSB 21 283*5113495bSYour Name #define MACTX_PHY_DESC_NSS_MSB 23 284*5113495bSYour Name #define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000 285*5113495bSYour Name 286*5113495bSYour Name #define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008 287*5113495bSYour Name #define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 288*5113495bSYour Name #define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 289*5113495bSYour Name #define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000 290*5113495bSYour Name 291*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008 292*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2B_LSB 27 293*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2B_MSB 28 294*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000 295*5113495bSYour Name 296*5113495bSYour Name #define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008 297*5113495bSYour Name #define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 298*5113495bSYour Name #define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 299*5113495bSYour Name #define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000 300*5113495bSYour Name 301*5113495bSYour Name #define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008 302*5113495bSYour Name #define MACTX_PHY_DESC_MU_NDP_LSB 30 303*5113495bSYour Name #define MACTX_PHY_DESC_MU_NDP_MSB 30 304*5113495bSYour Name #define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000 305*5113495bSYour Name 306*5113495bSYour Name #define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008 307*5113495bSYour Name #define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 308*5113495bSYour Name #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 309*5113495bSYour Name #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000 310*5113495bSYour Name 311*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008 312*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32 313*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39 314*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000 315*5113495bSYour Name 316*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008 317*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40 318*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40 319*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000 320*5113495bSYour Name 321*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008 322*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41 323*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41 324*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000 325*5113495bSYour Name 326*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008 327*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_LSB 42 328*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_MSB 42 329*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000 330*5113495bSYour Name 331*5113495bSYour Name #define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008 332*5113495bSYour Name #define MACTX_PHY_DESC_CP_SETTING_LSB 43 333*5113495bSYour Name #define MACTX_PHY_DESC_CP_SETTING_MSB 44 334*5113495bSYour Name #define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000 335*5113495bSYour Name 336*5113495bSYour Name #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008 337*5113495bSYour Name #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45 338*5113495bSYour Name #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46 339*5113495bSYour Name #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000 340*5113495bSYour Name 341*5113495bSYour Name #define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008 342*5113495bSYour Name #define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47 343*5113495bSYour Name #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49 344*5113495bSYour Name #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000 345*5113495bSYour Name 346*5113495bSYour Name #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008 347*5113495bSYour Name #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50 348*5113495bSYour Name #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50 349*5113495bSYour Name #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000 350*5113495bSYour Name 351*5113495bSYour Name #define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008 352*5113495bSYour Name #define MACTX_PHY_DESC_LTF_SIZE_LSB 51 353*5113495bSYour Name #define MACTX_PHY_DESC_LTF_SIZE_MSB 52 354*5113495bSYour Name #define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000 355*5113495bSYour Name 356*5113495bSYour Name #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008 357*5113495bSYour Name #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53 358*5113495bSYour Name #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56 359*5113495bSYour Name #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000 360*5113495bSYour Name 361*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008 362*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_3C_LSB 57 363*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_3C_MSB 57 364*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000 365*5113495bSYour Name 366*5113495bSYour Name #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008 367*5113495bSYour Name #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 368*5113495bSYour Name #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 369*5113495bSYour Name #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 370*5113495bSYour Name 371*5113495bSYour Name #endif 372