1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _MACTX_PHY_DESC_H_ 21 #define _MACTX_PHY_DESC_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #define NUM_OF_DWORDS_MACTX_PHY_DESC 4 26 27 #define NUM_OF_QWORDS_MACTX_PHY_DESC 2 28 29 struct mactx_phy_desc { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t reserved_0a : 16, 32 bf_type : 2, 33 wait_sifs : 2, 34 dot11b_preamble_type : 1, 35 pkt_type : 4, 36 su_or_mu : 2, 37 mu_type : 1, 38 bandwidth : 3, 39 channel_capture : 1; 40 uint32_t mcs : 4, 41 global_ofdma_mimo_enable : 1, 42 reserved_1a : 1, 43 stbc : 1, 44 dot11ax_su_extended : 1, 45 dot11ax_trigger_frame_embedded : 1, 46 tx_pwr_shared : 8, 47 tx_pwr_unshared : 8, 48 measure_power : 1, 49 tpc_glut_self_cal : 1, 50 back_to_back_transmission_expected : 1, 51 heavy_clip_nss : 3, 52 txbf_per_packet_no_csd_no_walsh : 1; 53 uint32_t ndp : 2, 54 ul_flag : 1, 55 triggered : 1, 56 ap_pkt_bw : 3, 57 ru_position_start : 8, 58 pcu_ppdu_setup_start_reason : 3, 59 tlv_source : 1, 60 reserved_2a : 2, 61 nss : 3, 62 stream_offset : 3, 63 reserved_2b : 2, 64 clpc_enable : 1, 65 mu_ndp : 1, 66 response_expected : 1; 67 uint32_t rx_chain_mask : 8, 68 rx_chain_mask_valid : 1, 69 ant_sel_valid : 1, 70 ant_sel : 1, 71 cp_setting : 2, 72 he_ppdu_subtype : 2, 73 active_channel : 3, 74 generate_phyrx_tx_start_timing : 1, 75 ltf_size : 2, 76 ru_size_updated_v2 : 4, 77 reserved_3c : 1, 78 u_sig_puncture_pattern_encoding : 6; 79 #else 80 uint32_t channel_capture : 1, 81 bandwidth : 3, 82 mu_type : 1, 83 su_or_mu : 2, 84 pkt_type : 4, 85 dot11b_preamble_type : 1, 86 wait_sifs : 2, 87 bf_type : 2, 88 reserved_0a : 16; 89 uint32_t txbf_per_packet_no_csd_no_walsh : 1, 90 heavy_clip_nss : 3, 91 back_to_back_transmission_expected : 1, 92 tpc_glut_self_cal : 1, 93 measure_power : 1, 94 tx_pwr_unshared : 8, 95 tx_pwr_shared : 8, 96 dot11ax_trigger_frame_embedded : 1, 97 dot11ax_su_extended : 1, 98 stbc : 1, 99 reserved_1a : 1, 100 global_ofdma_mimo_enable : 1, 101 mcs : 4; 102 uint32_t response_expected : 1, 103 mu_ndp : 1, 104 clpc_enable : 1, 105 reserved_2b : 2, 106 stream_offset : 3, 107 nss : 3, 108 reserved_2a : 2, 109 tlv_source : 1, 110 pcu_ppdu_setup_start_reason : 3, 111 ru_position_start : 8, 112 ap_pkt_bw : 3, 113 triggered : 1, 114 ul_flag : 1, 115 ndp : 2; 116 uint32_t u_sig_puncture_pattern_encoding : 6, 117 reserved_3c : 1, 118 ru_size_updated_v2 : 4, 119 ltf_size : 2, 120 generate_phyrx_tx_start_timing : 1, 121 active_channel : 3, 122 he_ppdu_subtype : 2, 123 cp_setting : 2, 124 ant_sel : 1, 125 ant_sel_valid : 1, 126 rx_chain_mask_valid : 1, 127 rx_chain_mask : 8; 128 #endif 129 }; 130 131 #define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000 132 #define MACTX_PHY_DESC_RESERVED_0A_LSB 0 133 #define MACTX_PHY_DESC_RESERVED_0A_MSB 15 134 #define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff 135 136 #define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000 137 #define MACTX_PHY_DESC_BF_TYPE_LSB 16 138 #define MACTX_PHY_DESC_BF_TYPE_MSB 17 139 #define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000 140 141 #define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000 142 #define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 143 #define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 144 #define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000 145 146 #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000 147 #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 148 #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 149 #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000 150 151 #define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000 152 #define MACTX_PHY_DESC_PKT_TYPE_LSB 21 153 #define MACTX_PHY_DESC_PKT_TYPE_MSB 24 154 #define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000 155 156 #define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000 157 #define MACTX_PHY_DESC_SU_OR_MU_LSB 25 158 #define MACTX_PHY_DESC_SU_OR_MU_MSB 26 159 #define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000 160 161 #define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000 162 #define MACTX_PHY_DESC_MU_TYPE_LSB 27 163 #define MACTX_PHY_DESC_MU_TYPE_MSB 27 164 #define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000 165 166 #define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000 167 #define MACTX_PHY_DESC_BANDWIDTH_LSB 28 168 #define MACTX_PHY_DESC_BANDWIDTH_MSB 30 169 #define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000 170 171 #define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000 172 #define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 173 #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 174 #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000 175 176 #define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000 177 #define MACTX_PHY_DESC_MCS_LSB 32 178 #define MACTX_PHY_DESC_MCS_MSB 35 179 #define MACTX_PHY_DESC_MCS_MASK 0x0000000f00000000 180 181 #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000 182 #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 36 183 #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 36 184 #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000001000000000 185 186 #define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x0000000000000000 187 #define MACTX_PHY_DESC_RESERVED_1A_LSB 37 188 #define MACTX_PHY_DESC_RESERVED_1A_MSB 37 189 #define MACTX_PHY_DESC_RESERVED_1A_MASK 0x0000002000000000 190 191 #define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000 192 #define MACTX_PHY_DESC_STBC_LSB 38 193 #define MACTX_PHY_DESC_STBC_MSB 38 194 #define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000 195 196 #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 197 #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39 198 #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39 199 #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000 200 201 #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000 202 #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40 203 #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40 204 #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000 205 206 #define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000 207 #define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41 208 #define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48 209 #define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000 210 211 #define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000 212 #define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49 213 #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56 214 #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000 215 216 #define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000 217 #define MACTX_PHY_DESC_MEASURE_POWER_LSB 57 218 #define MACTX_PHY_DESC_MEASURE_POWER_MSB 57 219 #define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000 220 221 #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000 222 #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58 223 #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58 224 #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000 225 226 #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000 227 #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59 228 #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59 229 #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000 230 231 #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000 232 #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60 233 #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62 234 #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000 235 236 #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000 237 #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63 238 #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63 239 #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000 240 241 #define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008 242 #define MACTX_PHY_DESC_NDP_LSB 0 243 #define MACTX_PHY_DESC_NDP_MSB 1 244 #define MACTX_PHY_DESC_NDP_MASK 0x0000000000000003 245 246 #define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008 247 #define MACTX_PHY_DESC_UL_FLAG_LSB 2 248 #define MACTX_PHY_DESC_UL_FLAG_MSB 2 249 #define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000004 250 251 #define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008 252 #define MACTX_PHY_DESC_TRIGGERED_LSB 3 253 #define MACTX_PHY_DESC_TRIGGERED_MSB 3 254 #define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000008 255 256 #define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008 257 #define MACTX_PHY_DESC_AP_PKT_BW_LSB 4 258 #define MACTX_PHY_DESC_AP_PKT_BW_MSB 6 259 #define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x0000000000000070 260 261 #define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008 262 #define MACTX_PHY_DESC_RU_POSITION_START_LSB 7 263 #define MACTX_PHY_DESC_RU_POSITION_START_MSB 14 264 #define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x0000000000007f80 265 266 #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008 267 #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15 268 #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17 269 #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000038000 270 271 #define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008 272 #define MACTX_PHY_DESC_TLV_SOURCE_LSB 18 273 #define MACTX_PHY_DESC_TLV_SOURCE_MSB 18 274 #define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000040000 275 276 #define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008 277 #define MACTX_PHY_DESC_RESERVED_2A_LSB 19 278 #define MACTX_PHY_DESC_RESERVED_2A_MSB 20 279 #define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000180000 280 281 #define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008 282 #define MACTX_PHY_DESC_NSS_LSB 21 283 #define MACTX_PHY_DESC_NSS_MSB 23 284 #define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000 285 286 #define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008 287 #define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 288 #define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 289 #define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000 290 291 #define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008 292 #define MACTX_PHY_DESC_RESERVED_2B_LSB 27 293 #define MACTX_PHY_DESC_RESERVED_2B_MSB 28 294 #define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000 295 296 #define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008 297 #define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 298 #define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 299 #define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000 300 301 #define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008 302 #define MACTX_PHY_DESC_MU_NDP_LSB 30 303 #define MACTX_PHY_DESC_MU_NDP_MSB 30 304 #define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000 305 306 #define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008 307 #define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 308 #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 309 #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000 310 311 #define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008 312 #define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32 313 #define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39 314 #define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000 315 316 #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008 317 #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40 318 #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40 319 #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000 320 321 #define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008 322 #define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41 323 #define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41 324 #define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000 325 326 #define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008 327 #define MACTX_PHY_DESC_ANT_SEL_LSB 42 328 #define MACTX_PHY_DESC_ANT_SEL_MSB 42 329 #define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000 330 331 #define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008 332 #define MACTX_PHY_DESC_CP_SETTING_LSB 43 333 #define MACTX_PHY_DESC_CP_SETTING_MSB 44 334 #define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000 335 336 #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008 337 #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45 338 #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46 339 #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000 340 341 #define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008 342 #define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47 343 #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49 344 #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000 345 346 #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008 347 #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50 348 #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50 349 #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000 350 351 #define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008 352 #define MACTX_PHY_DESC_LTF_SIZE_LSB 51 353 #define MACTX_PHY_DESC_LTF_SIZE_MSB 52 354 #define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000 355 356 #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008 357 #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53 358 #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56 359 #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000 360 361 #define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008 362 #define MACTX_PHY_DESC_RESERVED_3C_LSB 57 363 #define MACTX_PHY_DESC_RESERVED_3C_MSB 57 364 #define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000 365 366 #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008 367 #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 368 #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 369 #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 370 371 #endif 372