1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _MACTX_USER_DESC_COMMON_H_ 21 #define _MACTX_USER_DESC_COMMON_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #include "unallocated_ru_160_info.h" 26 #include "ru_allocation_160_info.h" 27 #define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 28 29 #define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8 30 31 struct mactx_user_desc_common { 32 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 33 uint32_t num_users : 6, 34 reserved_0b : 5, 35 ltf_size : 2, 36 reserved_0c : 3, 37 he_stf_long : 1, 38 reserved_0d : 7, 39 num_users_he_sigb_band0 : 8; 40 uint32_t num_ltf_symbols : 3, 41 reserved_1a : 5, 42 num_users_he_sigb_band1 : 8, 43 reserved_1b : 16; 44 uint32_t packet_extension_a_factor : 2, 45 packet_extension_pe_disambiguity : 1, 46 packet_extension : 3, 47 reserved : 2, 48 he_sigb_dcm : 1, 49 reserved_2b : 7, 50 he_sigb_compression : 1, 51 reserved_2c : 15; 52 uint32_t he_sigb_0_mcs : 3, 53 reserved_3a : 13, 54 num_he_sigb_sym : 5, 55 center_ru_0 : 1, 56 center_ru_1 : 1, 57 reserved_3b : 1, 58 ftm_en : 1, 59 pe_nss : 3, 60 pe_ltf_size : 2, 61 pe_content : 1, 62 pe_chain_csd_en : 1; 63 struct ru_allocation_160_info ru_allocation_0123_details; 64 struct ru_allocation_160_info ru_allocation_4567_details; 65 struct unallocated_ru_160_info ru_allocation_160_0_details; 66 struct unallocated_ru_160_info ru_allocation_160_1_details; 67 uint32_t num_data_symbols : 16, 68 ndp_ru_tone_set_index : 7, 69 ndp_feedback_status : 1, 70 doppler_indication : 1, 71 reserved_14a : 7; 72 uint32_t spatial_reuse : 16, 73 reserved_15a : 16; 74 #else 75 uint32_t num_users_he_sigb_band0 : 8, 76 reserved_0d : 7, 77 he_stf_long : 1, 78 reserved_0c : 3, 79 ltf_size : 2, 80 reserved_0b : 5, 81 num_users : 6; 82 uint32_t reserved_1b : 16, 83 num_users_he_sigb_band1 : 8, 84 reserved_1a : 5, 85 num_ltf_symbols : 3; 86 uint32_t reserved_2c : 15, 87 he_sigb_compression : 1, 88 reserved_2b : 7, 89 he_sigb_dcm : 1, 90 reserved : 2, 91 packet_extension : 3, 92 packet_extension_pe_disambiguity : 1, 93 packet_extension_a_factor : 2; 94 uint32_t pe_chain_csd_en : 1, 95 pe_content : 1, 96 pe_ltf_size : 2, 97 pe_nss : 3, 98 ftm_en : 1, 99 reserved_3b : 1, 100 center_ru_1 : 1, 101 center_ru_0 : 1, 102 num_he_sigb_sym : 5, 103 reserved_3a : 13, 104 he_sigb_0_mcs : 3; 105 struct ru_allocation_160_info ru_allocation_0123_details; 106 struct ru_allocation_160_info ru_allocation_4567_details; 107 struct unallocated_ru_160_info ru_allocation_160_0_details; 108 struct unallocated_ru_160_info ru_allocation_160_1_details; 109 uint32_t reserved_14a : 7, 110 doppler_indication : 1, 111 ndp_feedback_status : 1, 112 ndp_ru_tone_set_index : 7, 113 num_data_symbols : 16; 114 uint32_t reserved_15a : 16, 115 spatial_reuse : 16; 116 #endif 117 }; 118 119 #define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x0000000000000000 120 #define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 121 #define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 122 #define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x000000000000003f 123 124 #define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x0000000000000000 125 #define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 126 #define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 127 #define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x00000000000007c0 128 129 #define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x0000000000000000 130 #define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 131 #define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 132 #define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x0000000000001800 133 134 #define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x0000000000000000 135 #define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 136 #define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 137 #define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x000000000000e000 138 139 #define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x0000000000000000 140 #define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 141 #define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 142 #define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x0000000000010000 143 144 #define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x0000000000000000 145 #define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 146 #define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 147 #define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x0000000000fe0000 148 149 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x0000000000000000 150 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 151 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 152 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0x00000000ff000000 153 154 #define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 155 #define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 32 156 #define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 34 157 #define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 158 159 #define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x0000000000000000 160 #define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 35 161 #define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 39 162 #define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f800000000 163 164 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x0000000000000000 165 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 40 166 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 47 167 #define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff0000000000 168 169 #define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x0000000000000000 170 #define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 48 171 #define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 63 172 #define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff000000000000 173 174 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 175 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 176 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 177 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 178 179 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 180 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 181 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 182 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 183 184 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x0000000000000008 185 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 186 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 187 #define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x0000000000000038 188 189 #define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x0000000000000008 190 #define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 191 #define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 192 #define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x00000000000000c0 193 194 #define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x0000000000000008 195 #define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 196 #define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 197 #define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x0000000000000100 198 199 #define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x0000000000000008 200 #define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 201 #define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 202 #define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x000000000000fe00 203 204 #define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x0000000000000008 205 #define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 206 #define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 207 #define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x0000000000010000 208 209 #define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x0000000000000008 210 #define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 211 #define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 212 #define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0x00000000fffe0000 213 214 #define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000000000008 215 #define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 32 216 #define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 34 217 #define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x0000000700000000 218 219 #define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000000000008 220 #define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 35 221 #define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 47 222 #define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff800000000 223 224 #define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000008 225 #define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 48 226 #define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 52 227 #define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f000000000000 228 229 #define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000000000008 230 #define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 53 231 #define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 53 232 #define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x0020000000000000 233 234 #define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000000000008 235 #define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 54 236 #define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 54 237 #define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x0040000000000000 238 239 #define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000000000008 240 #define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 55 241 #define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 55 242 #define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x0080000000000000 243 244 #define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000000000008 245 #define MACTX_USER_DESC_COMMON_FTM_EN_LSB 56 246 #define MACTX_USER_DESC_COMMON_FTM_EN_MSB 56 247 #define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x0100000000000000 248 249 #define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000000000008 250 #define MACTX_USER_DESC_COMMON_PE_NSS_LSB 57 251 #define MACTX_USER_DESC_COMMON_PE_NSS_MSB 59 252 #define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e00000000000000 253 254 #define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000000000008 255 #define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 60 256 #define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 61 257 #define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x3000000000000000 258 259 #define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000000000008 260 #define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 62 261 #define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 62 262 #define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x4000000000000000 263 264 #define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000008 265 #define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 63 266 #define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 63 267 #define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 268 269 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010 270 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 271 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 272 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff 273 274 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010 275 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 276 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 277 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 278 279 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x0000000000000010 280 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 281 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 282 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 283 284 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010 285 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 286 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 287 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 288 289 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010 290 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 291 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 292 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 293 294 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010 295 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 296 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 297 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 298 299 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010 300 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 301 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 302 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 303 304 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x0000000000000010 305 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 50 306 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 63 307 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 308 309 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018 310 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 311 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 312 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff 313 314 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018 315 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 316 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 317 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 318 319 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x0000000000000018 320 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 321 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 322 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 323 324 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018 325 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 326 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 327 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 328 329 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018 330 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 331 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 332 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 333 334 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000000000000018 335 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 50 336 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 63 337 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 338 339 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020 340 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 341 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 342 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff 343 344 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020 345 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 346 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 347 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 348 349 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x0000000000000020 350 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 351 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 352 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 353 354 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020 355 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 356 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 357 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 358 359 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020 360 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 361 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 362 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 363 364 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020 365 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 366 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 367 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 368 369 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020 370 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 371 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 372 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 373 374 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x0000000000000020 375 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 50 376 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 63 377 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 378 379 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028 380 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 381 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 382 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff 383 384 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028 385 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 386 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 387 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 388 389 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x0000000000000028 390 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 391 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 392 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 393 394 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028 395 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 396 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 397 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 398 399 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028 400 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 401 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 402 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 403 404 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000000000000028 405 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 50 406 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 63 407 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 408 409 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 410 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 411 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 412 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x00000000000000ff 413 414 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 415 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 416 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 417 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x000000000000ff00 418 419 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 420 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 421 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 422 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x0000000000ff0000 423 424 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 425 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 426 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 427 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0x00000000ff000000 428 429 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 430 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 32 431 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 39 432 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff00000000 433 434 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 435 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 40 436 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 47 437 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff0000000000 438 439 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 440 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 48 441 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 55 442 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff000000000000 443 444 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 445 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 56 446 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 63 447 #define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff00000000000000 448 449 #define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000038 450 #define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 451 #define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 452 #define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x000000000000ffff 453 454 #define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x0000000000000038 455 #define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 456 #define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 457 #define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x00000000007f0000 458 459 #define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x0000000000000038 460 #define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 461 #define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 462 #define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x0000000000800000 463 464 #define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x0000000000000038 465 #define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 466 #define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 467 #define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x0000000001000000 468 469 #define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x0000000000000038 470 #define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 471 #define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 472 #define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0x00000000fe000000 473 474 #define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000000000000038 475 #define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 32 476 #define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 47 477 #define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff00000000 478 479 #define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000000000000038 480 #define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 48 481 #define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 63 482 #define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xffff000000000000 483 484 #endif 485