1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _MON_BUFFER_ADDR_H_ 21 #define _MON_BUFFER_ADDR_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #define NUM_OF_DWORDS_MON_BUFFER_ADDR 4 26 27 #define NUM_OF_QWORDS_MON_BUFFER_ADDR 2 28 29 struct mon_buffer_addr { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t buffer_virt_addr_31_0 : 32; 32 uint32_t buffer_virt_addr_63_32 : 32; 33 uint32_t dma_length : 12, 34 reserved_2a : 4, 35 msdu_continuation : 1, 36 truncated : 1, 37 reserved_2b : 14; 38 uint32_t tlv64_padding : 32; 39 #else 40 uint32_t buffer_virt_addr_31_0 : 32; 41 uint32_t buffer_virt_addr_63_32 : 32; 42 uint32_t reserved_2b : 14, 43 truncated : 1, 44 msdu_continuation : 1, 45 reserved_2a : 4, 46 dma_length : 12; 47 uint32_t tlv64_padding : 32; 48 #endif 49 }; 50 51 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000 52 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 53 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 54 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff 55 56 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000 57 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32 58 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63 59 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000 60 61 #define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008 62 #define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 63 #define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 64 #define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff 65 66 #define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008 67 #define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 68 #define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 69 #define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000 70 71 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008 72 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 73 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 74 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000 75 76 #define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008 77 #define MON_BUFFER_ADDR_TRUNCATED_LSB 17 78 #define MON_BUFFER_ADDR_TRUNCATED_MSB 17 79 #define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000 80 81 #define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008 82 #define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 83 #define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 84 #define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000 85 86 #define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008 87 #define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32 88 #define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63 89 #define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000 90 91 #endif 92