1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _MON_INGRESS_RING_H_ 21 #define _MON_INGRESS_RING_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #include "buffer_addr_info.h" 26 #define NUM_OF_DWORDS_MON_INGRESS_RING 4 27 28 struct mon_ingress_ring { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct buffer_addr_info buffer_addr_info_details; 31 uint32_t buffer_virt_addr_31_0 : 32; 32 uint32_t buffer_virt_addr_63_32 : 32; 33 #else 34 struct buffer_addr_info buffer_addr_info_details; 35 uint32_t buffer_virt_addr_31_0 : 32; 36 uint32_t buffer_virt_addr_63_32 : 32; 37 #endif 38 }; 39 40 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 41 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 42 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 43 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 44 45 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 46 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 47 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 48 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 49 50 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 51 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 52 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 53 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 54 55 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 56 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 57 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 58 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 59 60 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 61 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 62 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 63 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 64 65 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c 66 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 67 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 68 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 69 70 #endif 71