1*5113495bSYour Name 2*5113495bSYour Name /* 3*5113495bSYour Name * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4*5113495bSYour Name * 5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 6*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 7*5113495bSYour Name * above copyright notice and this permission notice appear in all 8*5113495bSYour Name * copies. 9*5113495bSYour Name * 10*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 18*5113495bSYour Name */ 19*5113495bSYour Name 20*5113495bSYour Name #ifndef __MSMHWIOBASE_H__ 21*5113495bSYour Name #define __MSMHWIOBASE_H__ 22*5113495bSYour Name 23*5113495bSYour Name #define WCSS_WCSS_BASE 0x00000000 24*5113495bSYour Name #define WCSS_WCSS_BASE_SIZE 0x01000000 25*5113495bSYour Name #define WCSS_WCSS_BASE_PHYS 0x00000000 26*5113495bSYour Name 27*5113495bSYour Name #define QDSS_STM_SIZE_BASE 0x00100000 28*5113495bSYour Name #define QDSS_STM_SIZE_BASE_SIZE 0x100000000 29*5113495bSYour Name #define QDSS_STM_SIZE_BASE_PHYS 0x00100000 30*5113495bSYour Name 31*5113495bSYour Name #define BOOT_ROM_SIZE_BASE 0x00200000 32*5113495bSYour Name #define BOOT_ROM_SIZE_BASE_SIZE 0x100000000 33*5113495bSYour Name #define BOOT_ROM_SIZE_BASE_PHYS 0x00200000 34*5113495bSYour Name 35*5113495bSYour Name #define SYSTEM_IRAM_SIZE_BASE 0x00400000 36*5113495bSYour Name #define SYSTEM_IRAM_SIZE_BASE_SIZE 0x100000000 37*5113495bSYour Name #define SYSTEM_IRAM_SIZE_BASE_PHYS 0x00400000 38*5113495bSYour Name 39*5113495bSYour Name #define BOOT_ROM_START_ADDRESS_BASE 0x01200000 40*5113495bSYour Name #define BOOT_ROM_START_ADDRESS_BASE_SIZE 0x100000000 41*5113495bSYour Name #define BOOT_ROM_START_ADDRESS_BASE_PHYS 0x01200000 42*5113495bSYour Name 43*5113495bSYour Name #define BOOT_ROM_END_ADDRESS_BASE 0x013fffff 44*5113495bSYour Name #define BOOT_ROM_END_ADDRESS_BASE_SIZE 0x100000000 45*5113495bSYour Name #define BOOT_ROM_END_ADDRESS_BASE_PHYS 0x013fffff 46*5113495bSYour Name 47*5113495bSYour Name #define SYSTEM_IRAM_START_ADDRESS_BASE 0x01400000 48*5113495bSYour Name #define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE 0x100000000 49*5113495bSYour Name #define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS 0x01400000 50*5113495bSYour Name 51*5113495bSYour Name #define SYSTEM_IRAM_END_ADDRESS_BASE 0x017fffff 52*5113495bSYour Name #define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE 0x100000000 53*5113495bSYour Name #define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS 0x017fffff 54*5113495bSYour Name 55*5113495bSYour Name #define QDSS_STM_BASE 0x01800000 56*5113495bSYour Name #define QDSS_STM_BASE_SIZE 0x100000000 57*5113495bSYour Name #define QDSS_STM_BASE_PHYS 0x01800000 58*5113495bSYour Name 59*5113495bSYour Name #define QDSS_STM_END_BASE 0x018fffff 60*5113495bSYour Name #define QDSS_STM_END_BASE_SIZE 0x100000000 61*5113495bSYour Name #define QDSS_STM_END_BASE_PHYS 0x018fffff 62*5113495bSYour Name 63*5113495bSYour Name #define TLMM_BASE 0x01900000 64*5113495bSYour Name #define TLMM_BASE_SIZE 0x00200000 65*5113495bSYour Name #define TLMM_BASE_PHYS 0x01900000 66*5113495bSYour Name 67*5113495bSYour Name #define CORE_TOP_CSR_BASE 0x01b00000 68*5113495bSYour Name #define CORE_TOP_CSR_BASE_SIZE 0x00040000 69*5113495bSYour Name #define CORE_TOP_CSR_BASE_PHYS 0x01b00000 70*5113495bSYour Name 71*5113495bSYour Name #define BLSP1_BLSP_BASE 0x01b40000 72*5113495bSYour Name #define BLSP1_BLSP_BASE_SIZE 0x00040000 73*5113495bSYour Name #define BLSP1_BLSP_BASE_PHYS 0x01b40000 74*5113495bSYour Name 75*5113495bSYour Name #define SOC_WFSS_CE_REG_BASE 0x01b80000 76*5113495bSYour Name #define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000 77*5113495bSYour Name #define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000 78*5113495bSYour Name 79*5113495bSYour Name #define WL_TLMM_BASE 0x01bc0000 80*5113495bSYour Name #define WL_TLMM_BASE_SIZE 0x00020000 81*5113495bSYour Name #define WL_TLMM_BASE_PHYS 0x01bc0000 82*5113495bSYour Name 83*5113495bSYour Name #define MEMSS_CSR_BASE 0x01be0000 84*5113495bSYour Name #define MEMSS_CSR_BASE_SIZE 0x0000001c 85*5113495bSYour Name #define MEMSS_CSR_BASE_PHYS 0x01be0000 86*5113495bSYour Name 87*5113495bSYour Name #define TSENS_SROT_BASE 0x01bf0000 88*5113495bSYour Name #define TSENS_SROT_BASE_SIZE 0x00001000 89*5113495bSYour Name #define TSENS_SROT_BASE_PHYS 0x01bf0000 90*5113495bSYour Name 91*5113495bSYour Name #define TSENS_TM_BASE 0x01bf1000 92*5113495bSYour Name #define TSENS_TM_BASE_SIZE 0x00001000 93*5113495bSYour Name #define TSENS_TM_BASE_PHYS 0x01bf1000 94*5113495bSYour Name 95*5113495bSYour Name #define QDSS_APB_DEC_QDSS_APB_BASE 0x01c00000 96*5113495bSYour Name #define QDSS_APB_DEC_QDSS_APB_BASE_SIZE 0x00080000 97*5113495bSYour Name #define QDSS_APB_DEC_QDSS_APB_BASE_PHYS 0x01c00000 98*5113495bSYour Name 99*5113495bSYour Name #define QDSS_WRAPPER_TOP_BASE 0x01c80000 100*5113495bSYour Name #define QDSS_WRAPPER_TOP_BASE_SIZE 0x0007fffd 101*5113495bSYour Name #define QDSS_WRAPPER_TOP_BASE_PHYS 0x01c80000 102*5113495bSYour Name 103*5113495bSYour Name #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE 0x01d00000 104*5113495bSYour Name #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE 0x00100000 105*5113495bSYour Name #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS 0x01d00000 106*5113495bSYour Name 107*5113495bSYour Name #define PCIE_PCIE_TOP_WRAPPER_BASE 0x01e00000 108*5113495bSYour Name #define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000 109*5113495bSYour Name #define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000 110*5113495bSYour Name 111*5113495bSYour Name #define SECURITY_CONTROL_WLAN_BASE 0x01e20000 112*5113495bSYour Name #define SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000 113*5113495bSYour Name #define SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000 114*5113495bSYour Name 115*5113495bSYour Name #define EDPD_CAL_ACC_BASE 0x01e28000 116*5113495bSYour Name #define EDPD_CAL_ACC_BASE_SIZE 0x00003000 117*5113495bSYour Name #define EDPD_CAL_ACC_BASE_PHYS 0x01e28000 118*5113495bSYour Name 119*5113495bSYour Name #define CPR_CX_CPR3_BASE 0x01e30000 120*5113495bSYour Name #define CPR_CX_CPR3_BASE_SIZE 0x00004000 121*5113495bSYour Name #define CPR_CX_CPR3_BASE_PHYS 0x01e30000 122*5113495bSYour Name 123*5113495bSYour Name #define CPR_MX_CPR3_BASE 0x01e34000 124*5113495bSYour Name #define CPR_MX_CPR3_BASE_SIZE 0x00004000 125*5113495bSYour Name #define CPR_MX_CPR3_BASE_PHYS 0x01e34000 126*5113495bSYour Name 127*5113495bSYour Name #define GCC_GCC_BASE 0x01e40000 128*5113495bSYour Name #define GCC_GCC_BASE_SIZE 0x000003e8 129*5113495bSYour Name #define GCC_GCC_BASE_PHYS 0x01e40000 130*5113495bSYour Name 131*5113495bSYour Name #define PRNG_PRNG_TOP_BASE 0x01e50000 132*5113495bSYour Name #define PRNG_PRNG_TOP_BASE_SIZE 0x00010000 133*5113495bSYour Name #define PRNG_PRNG_TOP_BASE_PHYS 0x01e50000 134*5113495bSYour Name 135*5113495bSYour Name #define PCNOC_0_BUS_TIMEOUT_BASE 0x01e60000 136*5113495bSYour Name #define PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000 137*5113495bSYour Name #define PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000 138*5113495bSYour Name 139*5113495bSYour Name #define PCNOC_1_BUS_TIMEOUT_BASE 0x01e61000 140*5113495bSYour Name #define PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000 141*5113495bSYour Name #define PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000 142*5113495bSYour Name 143*5113495bSYour Name #define PCNOC_2_BUS_TIMEOUT_BASE 0x01e62000 144*5113495bSYour Name #define PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000 145*5113495bSYour Name #define PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000 146*5113495bSYour Name 147*5113495bSYour Name #define PCNOC_3_BUS_TIMEOUT_BASE 0x01e63000 148*5113495bSYour Name #define PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000 149*5113495bSYour Name #define PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000 150*5113495bSYour Name 151*5113495bSYour Name #define RRI_PREFETCH_REG_BASE 0x01e70000 152*5113495bSYour Name #define RRI_PREFETCH_REG_BASE_SIZE 0x00010000 153*5113495bSYour Name #define RRI_PREFETCH_REG_BASE_PHYS 0x01e70000 154*5113495bSYour Name 155*5113495bSYour Name #define SYSTEM_NOC_BASE 0x01e80000 156*5113495bSYour Name #define SYSTEM_NOC_BASE_SIZE 0x0000a000 157*5113495bSYour Name #define SYSTEM_NOC_BASE_PHYS 0x01e80000 158*5113495bSYour Name 159*5113495bSYour Name #define PC_NOC_BASE 0x01f00000 160*5113495bSYour Name #define PC_NOC_BASE_SIZE 0x00003880 161*5113495bSYour Name #define PC_NOC_BASE_PHYS 0x01f00000 162*5113495bSYour Name 163*5113495bSYour Name #define WLAON_WL_AON_REG_BASE 0x01f80000 164*5113495bSYour Name #define WLAON_WL_AON_REG_BASE_SIZE 0x000007c8 165*5113495bSYour Name #define WLAON_WL_AON_REG_BASE_PHYS 0x01f80000 166*5113495bSYour Name 167*5113495bSYour Name #define SYSPM_SYSPM_REG_BASE 0x01f82000 168*5113495bSYour Name #define SYSPM_SYSPM_REG_BASE_SIZE 0x00001000 169*5113495bSYour Name #define SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000 170*5113495bSYour Name 171*5113495bSYour Name #define PMU_WLAN_PMU_TOP_BASE 0x01f88000 172*5113495bSYour Name #define PMU_WLAN_PMU_TOP_BASE_SIZE 0x00000340 173*5113495bSYour Name #define PMU_WLAN_PMU_TOP_BASE_PHYS 0x01f88000 174*5113495bSYour Name 175*5113495bSYour Name #define PMU_NOC_BASE 0x01f8a000 176*5113495bSYour Name #define PMU_NOC_BASE_SIZE 0x00000080 177*5113495bSYour Name #define PMU_NOC_BASE_PHYS 0x01f8a000 178*5113495bSYour Name 179*5113495bSYour Name #define PCIE_ATU_REGION_BASE 0x04000000 180*5113495bSYour Name #define PCIE_ATU_REGION_BASE_SIZE 0x100000000 181*5113495bSYour Name #define PCIE_ATU_REGION_BASE_PHYS 0x04000000 182*5113495bSYour Name 183*5113495bSYour Name #define PCIE_ATU_REGION_SIZE_BASE 0x40000000 184*5113495bSYour Name #define PCIE_ATU_REGION_SIZE_BASE_SIZE 0x100000000 185*5113495bSYour Name #define PCIE_ATU_REGION_SIZE_BASE_PHYS 0x40000000 186*5113495bSYour Name 187*5113495bSYour Name #define PCIE_ATU_REGION_END_BASE 0x43ffffff 188*5113495bSYour Name #define PCIE_ATU_REGION_END_BASE_SIZE 0x100000000 189*5113495bSYour Name #define PCIE_ATU_REGION_END_BASE_PHYS 0x43ffffff 190*5113495bSYour Name 191*5113495bSYour Name #endif 192