1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef __MSMHWIOBASE_H__ 21 #define __MSMHWIOBASE_H__ 22 23 #define WCSS_WCSS_BASE 0x00000000 24 #define WCSS_WCSS_BASE_SIZE 0x01000000 25 #define WCSS_WCSS_BASE_PHYS 0x00000000 26 27 #define QDSS_STM_SIZE_BASE 0x00100000 28 #define QDSS_STM_SIZE_BASE_SIZE 0x100000000 29 #define QDSS_STM_SIZE_BASE_PHYS 0x00100000 30 31 #define BOOT_ROM_SIZE_BASE 0x00200000 32 #define BOOT_ROM_SIZE_BASE_SIZE 0x100000000 33 #define BOOT_ROM_SIZE_BASE_PHYS 0x00200000 34 35 #define SYSTEM_IRAM_SIZE_BASE 0x00400000 36 #define SYSTEM_IRAM_SIZE_BASE_SIZE 0x100000000 37 #define SYSTEM_IRAM_SIZE_BASE_PHYS 0x00400000 38 39 #define BOOT_ROM_START_ADDRESS_BASE 0x01200000 40 #define BOOT_ROM_START_ADDRESS_BASE_SIZE 0x100000000 41 #define BOOT_ROM_START_ADDRESS_BASE_PHYS 0x01200000 42 43 #define BOOT_ROM_END_ADDRESS_BASE 0x013fffff 44 #define BOOT_ROM_END_ADDRESS_BASE_SIZE 0x100000000 45 #define BOOT_ROM_END_ADDRESS_BASE_PHYS 0x013fffff 46 47 #define SYSTEM_IRAM_START_ADDRESS_BASE 0x01400000 48 #define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE 0x100000000 49 #define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS 0x01400000 50 51 #define SYSTEM_IRAM_END_ADDRESS_BASE 0x017fffff 52 #define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE 0x100000000 53 #define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS 0x017fffff 54 55 #define QDSS_STM_BASE 0x01800000 56 #define QDSS_STM_BASE_SIZE 0x100000000 57 #define QDSS_STM_BASE_PHYS 0x01800000 58 59 #define QDSS_STM_END_BASE 0x018fffff 60 #define QDSS_STM_END_BASE_SIZE 0x100000000 61 #define QDSS_STM_END_BASE_PHYS 0x018fffff 62 63 #define TLMM_BASE 0x01900000 64 #define TLMM_BASE_SIZE 0x00200000 65 #define TLMM_BASE_PHYS 0x01900000 66 67 #define CORE_TOP_CSR_BASE 0x01b00000 68 #define CORE_TOP_CSR_BASE_SIZE 0x00040000 69 #define CORE_TOP_CSR_BASE_PHYS 0x01b00000 70 71 #define BLSP1_BLSP_BASE 0x01b40000 72 #define BLSP1_BLSP_BASE_SIZE 0x00040000 73 #define BLSP1_BLSP_BASE_PHYS 0x01b40000 74 75 #define SOC_WFSS_CE_REG_BASE 0x01b80000 76 #define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000 77 #define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000 78 79 #define WL_TLMM_BASE 0x01bc0000 80 #define WL_TLMM_BASE_SIZE 0x00020000 81 #define WL_TLMM_BASE_PHYS 0x01bc0000 82 83 #define MEMSS_CSR_BASE 0x01be0000 84 #define MEMSS_CSR_BASE_SIZE 0x0000001c 85 #define MEMSS_CSR_BASE_PHYS 0x01be0000 86 87 #define TSENS_SROT_BASE 0x01bf0000 88 #define TSENS_SROT_BASE_SIZE 0x00001000 89 #define TSENS_SROT_BASE_PHYS 0x01bf0000 90 91 #define TSENS_TM_BASE 0x01bf1000 92 #define TSENS_TM_BASE_SIZE 0x00001000 93 #define TSENS_TM_BASE_PHYS 0x01bf1000 94 95 #define QDSS_APB_DEC_QDSS_APB_BASE 0x01c00000 96 #define QDSS_APB_DEC_QDSS_APB_BASE_SIZE 0x00080000 97 #define QDSS_APB_DEC_QDSS_APB_BASE_PHYS 0x01c00000 98 99 #define QDSS_WRAPPER_TOP_BASE 0x01c80000 100 #define QDSS_WRAPPER_TOP_BASE_SIZE 0x0007fffd 101 #define QDSS_WRAPPER_TOP_BASE_PHYS 0x01c80000 102 103 #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE 0x01d00000 104 #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE 0x00100000 105 #define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS 0x01d00000 106 107 #define PCIE_PCIE_TOP_WRAPPER_BASE 0x01e00000 108 #define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000 109 #define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000 110 111 #define SECURITY_CONTROL_WLAN_BASE 0x01e20000 112 #define SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000 113 #define SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000 114 115 #define EDPD_CAL_ACC_BASE 0x01e28000 116 #define EDPD_CAL_ACC_BASE_SIZE 0x00003000 117 #define EDPD_CAL_ACC_BASE_PHYS 0x01e28000 118 119 #define CPR_CX_CPR3_BASE 0x01e30000 120 #define CPR_CX_CPR3_BASE_SIZE 0x00004000 121 #define CPR_CX_CPR3_BASE_PHYS 0x01e30000 122 123 #define CPR_MX_CPR3_BASE 0x01e34000 124 #define CPR_MX_CPR3_BASE_SIZE 0x00004000 125 #define CPR_MX_CPR3_BASE_PHYS 0x01e34000 126 127 #define GCC_GCC_BASE 0x01e40000 128 #define GCC_GCC_BASE_SIZE 0x000003e8 129 #define GCC_GCC_BASE_PHYS 0x01e40000 130 131 #define PRNG_PRNG_TOP_BASE 0x01e50000 132 #define PRNG_PRNG_TOP_BASE_SIZE 0x00010000 133 #define PRNG_PRNG_TOP_BASE_PHYS 0x01e50000 134 135 #define PCNOC_0_BUS_TIMEOUT_BASE 0x01e60000 136 #define PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000 137 #define PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000 138 139 #define PCNOC_1_BUS_TIMEOUT_BASE 0x01e61000 140 #define PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000 141 #define PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000 142 143 #define PCNOC_2_BUS_TIMEOUT_BASE 0x01e62000 144 #define PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000 145 #define PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000 146 147 #define PCNOC_3_BUS_TIMEOUT_BASE 0x01e63000 148 #define PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000 149 #define PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000 150 151 #define RRI_PREFETCH_REG_BASE 0x01e70000 152 #define RRI_PREFETCH_REG_BASE_SIZE 0x00010000 153 #define RRI_PREFETCH_REG_BASE_PHYS 0x01e70000 154 155 #define SYSTEM_NOC_BASE 0x01e80000 156 #define SYSTEM_NOC_BASE_SIZE 0x0000a000 157 #define SYSTEM_NOC_BASE_PHYS 0x01e80000 158 159 #define PC_NOC_BASE 0x01f00000 160 #define PC_NOC_BASE_SIZE 0x00003880 161 #define PC_NOC_BASE_PHYS 0x01f00000 162 163 #define WLAON_WL_AON_REG_BASE 0x01f80000 164 #define WLAON_WL_AON_REG_BASE_SIZE 0x000007c8 165 #define WLAON_WL_AON_REG_BASE_PHYS 0x01f80000 166 167 #define SYSPM_SYSPM_REG_BASE 0x01f82000 168 #define SYSPM_SYSPM_REG_BASE_SIZE 0x00001000 169 #define SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000 170 171 #define PMU_WLAN_PMU_TOP_BASE 0x01f88000 172 #define PMU_WLAN_PMU_TOP_BASE_SIZE 0x00000340 173 #define PMU_WLAN_PMU_TOP_BASE_PHYS 0x01f88000 174 175 #define PMU_NOC_BASE 0x01f8a000 176 #define PMU_NOC_BASE_SIZE 0x00000080 177 #define PMU_NOC_BASE_PHYS 0x01f8a000 178 179 #define PCIE_ATU_REGION_BASE 0x04000000 180 #define PCIE_ATU_REGION_BASE_SIZE 0x100000000 181 #define PCIE_ATU_REGION_BASE_PHYS 0x04000000 182 183 #define PCIE_ATU_REGION_SIZE_BASE 0x40000000 184 #define PCIE_ATU_REGION_SIZE_BASE_SIZE 0x100000000 185 #define PCIE_ATU_REGION_SIZE_BASE_PHYS 0x40000000 186 187 #define PCIE_ATU_REGION_END_BASE 0x43ffffff 188 #define PCIE_ATU_REGION_END_BASE_SIZE 0x100000000 189 #define PCIE_ATU_REGION_END_BASE_PHYS 0x43ffffff 190 191 #endif 192