1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 #ifndef _OFDMA_TRIGGER_DETAILS_H_ 21 #define _OFDMA_TRIGGER_DETAILS_H_ 22 #if !defined(__ASSEMBLER__) 23 #endif 24 25 #include "mlo_sta_id_details.h" 26 #define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 22 27 28 #define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 11 29 30 struct ofdma_trigger_details { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 uint32_t ax_trigger_source : 1, 33 rx_trigger_frame_user_source : 2, 34 received_bandwidth : 3, 35 txop_duration_all_ones : 1, 36 eht_trigger_response : 1, 37 pre_rssi_comb : 8, 38 rssi_comb : 8, 39 rxpcu_pcie_l0_req_duration : 8; 40 uint32_t he_trigger_ul_ppdu_length : 5, 41 he_trigger_ru_allocation : 8, 42 he_trigger_dl_tx_power : 5, 43 he_trigger_ul_target_rssi : 5, 44 he_trigger_ul_mcs : 2, 45 he_trigger_reserved : 1, 46 bss_color : 6; 47 uint32_t trigger_type : 4, 48 lsig_response_length : 12, 49 cascade_indication : 1, 50 carrier_sense : 1, 51 bandwidth : 2, 52 cp_ltf_size : 2, 53 mu_mimo_ltf_mode : 1, 54 number_of_ltfs : 3, 55 stbc : 1, 56 ldpc_extra_symbol : 1, 57 ap_tx_power_lsb_part : 4; 58 uint32_t ap_tx_power_msb_part : 2, 59 packet_extension_a_factor : 2, 60 packet_extension_pe_disambiguity : 1, 61 spatial_reuse : 16, 62 doppler : 1, 63 he_siga_reserved : 9, 64 reserved_3b : 1; 65 uint32_t aid12 : 12, 66 ru_allocation : 9, 67 mcs : 4, 68 dcm : 1, 69 start_spatial_stream : 3, 70 number_of_spatial_stream : 3; 71 uint32_t target_rssi : 7, 72 coding_type : 1, 73 mpdu_mu_spacing_factor : 2, 74 tid_aggregation_limit : 3, 75 reserved_5b : 1, 76 prefered_ac : 2, 77 bar_control_ack_policy : 1, 78 bar_control_multi_tid : 1, 79 bar_control_compressed_bitmap : 1, 80 bar_control_reserved : 9, 81 bar_control_tid_info : 4; 82 uint32_t nr0_per_tid_info_reserved : 12, 83 nr0_per_tid_info_tid_value : 4, 84 nr0_start_seq_ctrl_frag_number : 4, 85 nr0_start_seq_ctrl_start_seq_number : 12; 86 uint32_t nr1_per_tid_info_reserved : 12, 87 nr1_per_tid_info_tid_value : 4, 88 nr1_start_seq_ctrl_frag_number : 4, 89 nr1_start_seq_ctrl_start_seq_number : 12; 90 uint32_t nr2_per_tid_info_reserved : 12, 91 nr2_per_tid_info_tid_value : 4, 92 nr2_start_seq_ctrl_frag_number : 4, 93 nr2_start_seq_ctrl_start_seq_number : 12; 94 uint32_t nr3_per_tid_info_reserved : 12, 95 nr3_per_tid_info_tid_value : 4, 96 nr3_start_seq_ctrl_frag_number : 4, 97 nr3_start_seq_ctrl_start_seq_number : 12; 98 uint32_t nr4_per_tid_info_reserved : 12, 99 nr4_per_tid_info_tid_value : 4, 100 nr4_start_seq_ctrl_frag_number : 4, 101 nr4_start_seq_ctrl_start_seq_number : 12; 102 uint32_t nr5_per_tid_info_reserved : 12, 103 nr5_per_tid_info_tid_value : 4, 104 nr5_start_seq_ctrl_frag_number : 4, 105 nr5_start_seq_ctrl_start_seq_number : 12; 106 uint32_t nr6_per_tid_info_reserved : 12, 107 nr6_per_tid_info_tid_value : 4, 108 nr6_start_seq_ctrl_frag_number : 4, 109 nr6_start_seq_ctrl_start_seq_number : 12; 110 uint32_t nr7_per_tid_info_reserved : 12, 111 nr7_per_tid_info_tid_value : 4, 112 nr7_start_seq_ctrl_frag_number : 4, 113 nr7_start_seq_ctrl_start_seq_number : 12; 114 uint32_t fb_segment_retransmission_bitmap : 8, 115 reserved_14a : 2, 116 u_sig_puncture_pattern_encoding : 6, 117 dot11be_puncture_bitmap : 16; 118 uint32_t rx_chain_mask : 8, 119 rx_duration_field : 16, 120 scrambler_seed : 7, 121 rx_chain_mask_type : 1; 122 struct mlo_sta_id_details mlo_sta_id_details_rx; 123 uint16_t normalized_pre_rssi_comb : 8, 124 normalized_rssi_comb : 8; 125 uint32_t sw_peer_id : 16, 126 response_tx_duration : 16; 127 uint32_t __reserved_g_0005_trigger_subtype : 4, 128 tbr_trigger_common_info_79_68 : 12, 129 tbr_trigger_sound_reserved_20_12 : 9, 130 i2r_rep : 3, 131 tbr_trigger_sound_reserved_25_24 : 2, 132 reserved_18a : 1, 133 qos_null_only_response_tx : 1; 134 uint32_t tbr_trigger_sound_sac : 16, 135 reserved_19a : 8, 136 u_sig_reserved2 : 5, 137 reserved_19b : 3; 138 uint32_t eht_special_aid12 : 12, 139 phy_version : 3, 140 bandwidth_ext : 2, 141 eht_spatial_reuse : 8, 142 u_sig_reserved1 : 7; 143 uint32_t eht_trigger_special_user_info_71_40 : 32; 144 #else 145 uint32_t rxpcu_pcie_l0_req_duration : 8, 146 rssi_comb : 8, 147 pre_rssi_comb : 8, 148 eht_trigger_response : 1, 149 txop_duration_all_ones : 1, 150 received_bandwidth : 3, 151 rx_trigger_frame_user_source : 2, 152 ax_trigger_source : 1; 153 uint32_t bss_color : 6, 154 he_trigger_reserved : 1, 155 he_trigger_ul_mcs : 2, 156 he_trigger_ul_target_rssi : 5, 157 he_trigger_dl_tx_power : 5, 158 he_trigger_ru_allocation : 8, 159 he_trigger_ul_ppdu_length : 5; 160 uint32_t ap_tx_power_lsb_part : 4, 161 ldpc_extra_symbol : 1, 162 stbc : 1, 163 number_of_ltfs : 3, 164 mu_mimo_ltf_mode : 1, 165 cp_ltf_size : 2, 166 bandwidth : 2, 167 carrier_sense : 1, 168 cascade_indication : 1, 169 lsig_response_length : 12, 170 trigger_type : 4; 171 uint32_t reserved_3b : 1, 172 he_siga_reserved : 9, 173 doppler : 1, 174 spatial_reuse : 16, 175 packet_extension_pe_disambiguity : 1, 176 packet_extension_a_factor : 2, 177 ap_tx_power_msb_part : 2; 178 uint32_t number_of_spatial_stream : 3, 179 start_spatial_stream : 3, 180 dcm : 1, 181 mcs : 4, 182 ru_allocation : 9, 183 aid12 : 12; 184 uint32_t bar_control_tid_info : 4, 185 bar_control_reserved : 9, 186 bar_control_compressed_bitmap : 1, 187 bar_control_multi_tid : 1, 188 bar_control_ack_policy : 1, 189 prefered_ac : 2, 190 reserved_5b : 1, 191 tid_aggregation_limit : 3, 192 mpdu_mu_spacing_factor : 2, 193 coding_type : 1, 194 target_rssi : 7; 195 uint32_t nr0_start_seq_ctrl_start_seq_number : 12, 196 nr0_start_seq_ctrl_frag_number : 4, 197 nr0_per_tid_info_tid_value : 4, 198 nr0_per_tid_info_reserved : 12; 199 uint32_t nr1_start_seq_ctrl_start_seq_number : 12, 200 nr1_start_seq_ctrl_frag_number : 4, 201 nr1_per_tid_info_tid_value : 4, 202 nr1_per_tid_info_reserved : 12; 203 uint32_t nr2_start_seq_ctrl_start_seq_number : 12, 204 nr2_start_seq_ctrl_frag_number : 4, 205 nr2_per_tid_info_tid_value : 4, 206 nr2_per_tid_info_reserved : 12; 207 uint32_t nr3_start_seq_ctrl_start_seq_number : 12, 208 nr3_start_seq_ctrl_frag_number : 4, 209 nr3_per_tid_info_tid_value : 4, 210 nr3_per_tid_info_reserved : 12; 211 uint32_t nr4_start_seq_ctrl_start_seq_number : 12, 212 nr4_start_seq_ctrl_frag_number : 4, 213 nr4_per_tid_info_tid_value : 4, 214 nr4_per_tid_info_reserved : 12; 215 uint32_t nr5_start_seq_ctrl_start_seq_number : 12, 216 nr5_start_seq_ctrl_frag_number : 4, 217 nr5_per_tid_info_tid_value : 4, 218 nr5_per_tid_info_reserved : 12; 219 uint32_t nr6_start_seq_ctrl_start_seq_number : 12, 220 nr6_start_seq_ctrl_frag_number : 4, 221 nr6_per_tid_info_tid_value : 4, 222 nr6_per_tid_info_reserved : 12; 223 uint32_t nr7_start_seq_ctrl_start_seq_number : 12, 224 nr7_start_seq_ctrl_frag_number : 4, 225 nr7_per_tid_info_tid_value : 4, 226 nr7_per_tid_info_reserved : 12; 227 uint32_t dot11be_puncture_bitmap : 16, 228 u_sig_puncture_pattern_encoding : 6, 229 reserved_14a : 2, 230 fb_segment_retransmission_bitmap : 8; 231 uint32_t rx_chain_mask_type : 1, 232 scrambler_seed : 7, 233 rx_duration_field : 16, 234 rx_chain_mask : 8; 235 uint32_t normalized_rssi_comb : 8, 236 normalized_pre_rssi_comb : 8; 237 struct mlo_sta_id_details mlo_sta_id_details_rx; 238 uint32_t response_tx_duration : 16, 239 sw_peer_id : 16; 240 uint32_t qos_null_only_response_tx : 1, 241 reserved_18a : 1, 242 tbr_trigger_sound_reserved_25_24 : 2, 243 i2r_rep : 3, 244 tbr_trigger_sound_reserved_20_12 : 9, 245 tbr_trigger_common_info_79_68 : 12, 246 __reserved_g_0005_trigger_subtype : 4; 247 uint32_t reserved_19b : 3, 248 u_sig_reserved2 : 5, 249 reserved_19a : 8, 250 tbr_trigger_sound_sac : 16; 251 uint32_t u_sig_reserved1 : 7, 252 eht_spatial_reuse : 8, 253 bandwidth_ext : 2, 254 phy_version : 3, 255 eht_special_aid12 : 12; 256 uint32_t eht_trigger_special_user_info_71_40 : 32; 257 #endif 258 }; 259 260 #define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 261 #define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 262 #define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 263 #define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000001 264 265 #define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x0000000000000000 266 #define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 267 #define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 268 #define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x0000000000000006 269 270 #define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x0000000000000000 271 #define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 272 #define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 273 #define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x0000000000000038 274 275 #define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 276 #define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 277 #define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 278 #define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x0000000000000040 279 280 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x0000000000000000 281 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 282 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 283 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x0000000000000080 284 285 #define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x0000000000000000 286 #define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 287 #define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 288 #define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x000000000000ff00 289 290 #define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 291 #define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 292 #define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 293 #define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x0000000000ff0000 294 295 #define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x0000000000000000 296 #define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 297 #define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 298 #define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0x00000000ff000000 299 300 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x0000000000000000 301 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 32 302 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 36 303 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f00000000 304 305 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x0000000000000000 306 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 37 307 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 44 308 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe000000000 309 310 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x0000000000000000 311 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 45 312 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 49 313 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e00000000000 314 315 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x0000000000000000 316 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 50 317 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 54 318 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c000000000000 319 320 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x0000000000000000 321 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 55 322 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 56 323 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x0180000000000000 324 325 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x0000000000000000 326 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 57 327 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 57 328 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x0200000000000000 329 330 #define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x0000000000000000 331 #define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 58 332 #define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 63 333 #define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc00000000000000 334 335 #define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000008 336 #define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 337 #define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 338 #define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f 339 340 #define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000008 341 #define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 342 #define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 343 #define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x000000000000fff0 344 345 #define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x0000000000000008 346 #define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 347 #define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 348 #define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x0000000000010000 349 350 #define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x0000000000000008 351 #define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 352 #define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 353 #define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x0000000000020000 354 355 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x0000000000000008 356 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 357 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 358 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x00000000000c0000 359 360 #define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000008 361 #define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 362 #define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 363 #define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x0000000000300000 364 365 #define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x0000000000000008 366 #define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 367 #define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 368 #define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x0000000000400000 369 370 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x0000000000000008 371 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 372 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 373 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x0000000003800000 374 375 #define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x0000000000000008 376 #define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 377 #define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 378 #define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x0000000004000000 379 380 #define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 381 #define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 382 #define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 383 #define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000008000000 384 385 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x0000000000000008 386 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 387 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 388 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0x00000000f0000000 389 390 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000000000008 391 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 32 392 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 33 393 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x0000000300000000 394 395 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 396 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 34 397 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 35 398 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c00000000 399 400 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 401 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 36 402 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 36 403 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000001000000000 404 405 #define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000008 406 #define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 37 407 #define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 52 408 #define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe000000000 409 410 #define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000000000008 411 #define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 53 412 #define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 53 413 #define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x0020000000000000 414 415 #define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000000000008 416 #define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 54 417 #define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 62 418 #define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc0000000000000 419 420 #define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 421 #define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 63 422 #define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 63 423 #define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x8000000000000000 424 425 #define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x0000000000000010 426 #define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 427 #define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 428 #define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x0000000000000fff 429 430 #define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000010 431 #define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 432 #define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 433 #define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x00000000001ff000 434 435 #define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x0000000000000010 436 #define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 437 #define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 438 #define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x0000000001e00000 439 440 #define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x0000000000000010 441 #define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 442 #define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 443 #define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x0000000002000000 444 445 #define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x0000000000000010 446 #define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 447 #define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 448 #define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x000000001c000000 449 450 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x0000000000000010 451 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 452 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 453 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0x00000000e0000000 454 455 #define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x0000000000000010 456 #define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 32 457 #define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 38 458 #define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f00000000 459 460 #define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x0000000000000010 461 #define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 39 462 #define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 39 463 #define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x0000008000000000 464 465 #define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x0000000000000010 466 #define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 40 467 #define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 41 468 #define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x0000030000000000 469 470 #define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000010 471 #define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 42 472 #define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 44 473 #define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c0000000000 474 475 #define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x0000000000000010 476 #define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 45 477 #define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 45 478 #define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x0000200000000000 479 480 #define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x0000000000000010 481 #define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 46 482 #define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 47 483 #define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c00000000000 484 485 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x0000000000000010 486 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 48 487 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 48 488 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x0001000000000000 489 490 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x0000000000000010 491 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 49 492 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 49 493 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x0002000000000000 494 495 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x0000000000000010 496 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 50 497 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 50 498 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x0004000000000000 499 500 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x0000000000000010 501 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 51 502 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 59 503 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff8000000000000 504 505 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x0000000000000010 506 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 60 507 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 63 508 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf000000000000000 509 510 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 511 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 512 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 513 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff 514 515 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 516 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 517 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 518 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 519 520 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 521 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 522 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 523 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 524 525 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 526 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 527 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 528 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 529 530 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 531 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 32 532 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 43 533 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 534 535 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 536 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 44 537 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 47 538 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 539 540 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 541 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 542 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 543 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 544 545 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 546 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 547 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 548 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 549 550 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 551 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 552 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 553 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff 554 555 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 556 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 557 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 558 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 559 560 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 561 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 562 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 563 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 564 565 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 566 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 567 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 568 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 569 570 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 571 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 32 572 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 43 573 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 574 575 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 576 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 44 577 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 47 578 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 579 580 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 581 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 582 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 583 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 584 585 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 586 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 587 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 588 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 589 590 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 591 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 592 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 593 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff 594 595 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 596 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 597 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 598 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 599 600 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 601 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 602 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 603 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 604 605 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 606 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 607 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 608 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 609 610 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 611 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 32 612 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 43 613 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 614 615 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 616 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 44 617 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 47 618 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 619 620 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 621 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 622 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 623 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 624 625 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 626 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 627 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 628 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 629 630 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 631 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 632 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 633 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff 634 635 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 636 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 637 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 638 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 639 640 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 641 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 642 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 643 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 644 645 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 646 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 647 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 648 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 649 650 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 651 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 32 652 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 43 653 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 654 655 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 656 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 44 657 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 47 658 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 659 660 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 661 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 662 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 663 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 664 665 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 666 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 667 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 668 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 669 670 #define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x0000000000000038 671 #define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 672 #define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 673 #define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x00000000000000ff 674 675 #define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x0000000000000038 676 #define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 677 #define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 678 #define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x0000000000000300 679 680 #define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000038 681 #define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 682 #define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 683 #define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x000000000000fc00 684 685 #define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000038 686 #define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 687 #define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 688 #define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0x00000000ffff0000 689 690 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000038 691 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 32 692 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 39 693 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff00000000 694 695 #define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000000000000038 696 #define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 40 697 #define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 55 698 #define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff0000000000 699 700 #define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000038 701 #define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 56 702 #define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 62 703 #define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f00000000000000 704 705 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000038 706 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 63 707 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 63 708 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x8000000000000000 709 710 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 711 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 712 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 713 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff 714 715 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 716 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 717 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 718 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 719 720 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 721 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 722 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 723 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 724 725 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 726 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 727 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 728 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 729 730 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 731 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 732 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 733 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 734 735 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000000000000040 736 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 737 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 738 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 739 740 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x0000000000000040 741 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 742 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 743 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 744 745 #define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000040 746 #define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 747 #define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 748 #define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 749 750 #define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x0000000000000040 751 #define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 48 752 #define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 63 753 #define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff000000000000 754 755 #define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000048 756 #define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 0 757 #define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 3 758 #define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000000f 759 760 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x0000000000000048 761 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 762 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 763 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x000000000000fff0 764 765 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x0000000000000048 766 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 767 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 768 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x0000000001ff0000 769 770 #define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x0000000000000048 771 #define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 772 #define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 773 #define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x000000000e000000 774 775 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x0000000000000048 776 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 777 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 778 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x0000000030000000 779 780 #define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x0000000000000048 781 #define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 782 #define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 783 #define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x0000000040000000 784 785 #define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x0000000000000048 786 #define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 787 #define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 788 #define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x0000000080000000 789 790 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000000000000048 791 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 32 792 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 47 793 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff00000000 794 795 #define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000000000000048 796 #define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 48 797 #define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 55 798 #define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff000000000000 799 800 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000000000000048 801 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 56 802 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 60 803 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f00000000000000 804 805 #define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000000000000048 806 #define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 61 807 #define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 63 808 #define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe000000000000000 809 810 #define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x0000000000000050 811 #define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 812 #define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 813 #define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x0000000000000fff 814 815 #define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x0000000000000050 816 #define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 817 #define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 818 #define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x0000000000007000 819 820 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x0000000000000050 821 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 822 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 823 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x0000000000018000 824 825 #define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x0000000000000050 826 #define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 827 #define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 828 #define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x0000000001fe0000 829 830 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x0000000000000050 831 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 832 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 833 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0x00000000fe000000 834 835 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x0000000000000050 836 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 32 837 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 63 838 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff00000000 839 840 #endif 841