1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _PHYRX_HE_SIG_B1_MU_H_ 23 #define _PHYRX_HE_SIG_B1_MU_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "he_sig_b1_mu_info.h" 28 #define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2 29 30 #define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1 31 32 struct phyrx_he_sig_b1_mu { 33 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 34 struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; 35 uint32_t tlv64_padding : 32; 36 #else 37 struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; 38 uint32_t tlv64_padding : 32; 39 #endif 40 }; 41 42 #define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 43 #define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 44 #define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 45 #define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff 46 47 #define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 48 #define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 49 #define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 50 #define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 51 52 #define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 53 #define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 54 #define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 55 #define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 56 57 #define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 58 #define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 59 #define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 60 #define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 61 62 #endif 63