1*5113495bSYour Name 2*5113495bSYour Name /* 3*5113495bSYour Name * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4*5113495bSYour Name * 5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 6*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 7*5113495bSYour Name * above copyright notice and this permission notice appear in all 8*5113495bSYour Name * copies. 9*5113495bSYour Name * 10*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 18*5113495bSYour Name */ 19*5113495bSYour Name 20*5113495bSYour Name 21*5113495bSYour Name 22*5113495bSYour Name #ifndef _REO_FLUSH_CACHE_H_ 23*5113495bSYour Name #define _REO_FLUSH_CACHE_H_ 24*5113495bSYour Name #if !defined(__ASSEMBLER__) 25*5113495bSYour Name #endif 26*5113495bSYour Name 27*5113495bSYour Name #include "uniform_reo_cmd_header.h" 28*5113495bSYour Name #define NUM_OF_DWORDS_REO_FLUSH_CACHE 10 29*5113495bSYour Name 30*5113495bSYour Name #define NUM_OF_QWORDS_REO_FLUSH_CACHE 5 31*5113495bSYour Name 32*5113495bSYour Name struct reo_flush_cache { 33*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 34*5113495bSYour Name struct uniform_reo_cmd_header cmd_header; 35*5113495bSYour Name uint32_t flush_addr_31_0 : 32; 36*5113495bSYour Name uint32_t flush_addr_39_32 : 8, 37*5113495bSYour Name forward_all_mpdus_in_queue : 1, 38*5113495bSYour Name release_cache_block_index : 1, 39*5113495bSYour Name cache_block_resource_index : 2, 40*5113495bSYour Name flush_without_invalidate : 1, 41*5113495bSYour Name block_cache_usage_after_flush : 1, 42*5113495bSYour Name flush_entire_cache : 1, 43*5113495bSYour Name flush_queue_1k_desc : 1, 44*5113495bSYour Name reserved_2b : 16; 45*5113495bSYour Name uint32_t reserved_3a : 32; 46*5113495bSYour Name uint32_t reserved_4a : 32; 47*5113495bSYour Name uint32_t reserved_5a : 32; 48*5113495bSYour Name uint32_t reserved_6a : 32; 49*5113495bSYour Name uint32_t reserved_7a : 32; 50*5113495bSYour Name uint32_t reserved_8a : 32; 51*5113495bSYour Name uint32_t tlv64_padding : 32; 52*5113495bSYour Name #else 53*5113495bSYour Name struct uniform_reo_cmd_header cmd_header; 54*5113495bSYour Name uint32_t flush_addr_31_0 : 32; 55*5113495bSYour Name uint32_t reserved_2b : 16, 56*5113495bSYour Name flush_queue_1k_desc : 1, 57*5113495bSYour Name flush_entire_cache : 1, 58*5113495bSYour Name block_cache_usage_after_flush : 1, 59*5113495bSYour Name flush_without_invalidate : 1, 60*5113495bSYour Name cache_block_resource_index : 2, 61*5113495bSYour Name release_cache_block_index : 1, 62*5113495bSYour Name forward_all_mpdus_in_queue : 1, 63*5113495bSYour Name flush_addr_39_32 : 8; 64*5113495bSYour Name uint32_t reserved_3a : 32; 65*5113495bSYour Name uint32_t reserved_4a : 32; 66*5113495bSYour Name uint32_t reserved_5a : 32; 67*5113495bSYour Name uint32_t reserved_6a : 32; 68*5113495bSYour Name uint32_t reserved_7a : 32; 69*5113495bSYour Name uint32_t reserved_8a : 32; 70*5113495bSYour Name uint32_t tlv64_padding : 32; 71*5113495bSYour Name #endif 72*5113495bSYour Name }; 73*5113495bSYour Name 74*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 75*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 76*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 77*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 78*5113495bSYour Name 79*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 80*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 81*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 82*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 83*5113495bSYour Name 84*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 85*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 86*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 87*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 88*5113495bSYour Name 89*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000 90*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32 91*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63 92*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000 93*5113495bSYour Name 94*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008 95*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0 96*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7 97*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff 98*5113495bSYour Name 99*5113495bSYour Name #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008 100*5113495bSYour Name #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 101*5113495bSYour Name #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8 102*5113495bSYour Name #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100 103*5113495bSYour Name 104*5113495bSYour Name #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008 105*5113495bSYour Name #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9 106*5113495bSYour Name #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9 107*5113495bSYour Name #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200 108*5113495bSYour Name 109*5113495bSYour Name #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 110*5113495bSYour Name #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 111*5113495bSYour Name #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11 112*5113495bSYour Name #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00 113*5113495bSYour Name 114*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008 115*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12 116*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12 117*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000 118*5113495bSYour Name 119*5113495bSYour Name #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 120*5113495bSYour Name #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 121*5113495bSYour Name #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13 122*5113495bSYour Name #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000 123*5113495bSYour Name 124*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008 125*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14 126*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14 127*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000 128*5113495bSYour Name 129*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 130*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15 131*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15 132*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000 133*5113495bSYour Name 134*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008 135*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_2B_LSB 16 136*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_2B_MSB 31 137*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000 138*5113495bSYour Name 139*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 140*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_3A_LSB 32 141*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_3A_MSB 63 142*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000 143*5113495bSYour Name 144*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 145*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_4A_LSB 0 146*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_4A_MSB 31 147*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff 148*5113495bSYour Name 149*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 150*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_5A_LSB 32 151*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_5A_MSB 63 152*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000 153*5113495bSYour Name 154*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 155*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_6A_LSB 0 156*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_6A_MSB 31 157*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff 158*5113495bSYour Name 159*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 160*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_7A_LSB 32 161*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_7A_MSB 63 162*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000 163*5113495bSYour Name 164*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 165*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_8A_LSB 0 166*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_8A_MSB 31 167*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff 168*5113495bSYour Name 169*5113495bSYour Name #define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 170*5113495bSYour Name #define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32 171*5113495bSYour Name #define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63 172*5113495bSYour Name #define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 173*5113495bSYour Name 174*5113495bSYour Name #endif 175