1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _REO_FLUSH_CACHE_H_ 23 #define _REO_FLUSH_CACHE_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "uniform_reo_cmd_header.h" 28 #define NUM_OF_DWORDS_REO_FLUSH_CACHE 10 29 30 #define NUM_OF_QWORDS_REO_FLUSH_CACHE 5 31 32 struct reo_flush_cache { 33 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 34 struct uniform_reo_cmd_header cmd_header; 35 uint32_t flush_addr_31_0 : 32; 36 uint32_t flush_addr_39_32 : 8, 37 forward_all_mpdus_in_queue : 1, 38 release_cache_block_index : 1, 39 cache_block_resource_index : 2, 40 flush_without_invalidate : 1, 41 block_cache_usage_after_flush : 1, 42 flush_entire_cache : 1, 43 flush_queue_1k_desc : 1, 44 reserved_2b : 16; 45 uint32_t reserved_3a : 32; 46 uint32_t reserved_4a : 32; 47 uint32_t reserved_5a : 32; 48 uint32_t reserved_6a : 32; 49 uint32_t reserved_7a : 32; 50 uint32_t reserved_8a : 32; 51 uint32_t tlv64_padding : 32; 52 #else 53 struct uniform_reo_cmd_header cmd_header; 54 uint32_t flush_addr_31_0 : 32; 55 uint32_t reserved_2b : 16, 56 flush_queue_1k_desc : 1, 57 flush_entire_cache : 1, 58 block_cache_usage_after_flush : 1, 59 flush_without_invalidate : 1, 60 cache_block_resource_index : 2, 61 release_cache_block_index : 1, 62 forward_all_mpdus_in_queue : 1, 63 flush_addr_39_32 : 8; 64 uint32_t reserved_3a : 32; 65 uint32_t reserved_4a : 32; 66 uint32_t reserved_5a : 32; 67 uint32_t reserved_6a : 32; 68 uint32_t reserved_7a : 32; 69 uint32_t reserved_8a : 32; 70 uint32_t tlv64_padding : 32; 71 #endif 72 }; 73 74 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 75 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 76 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 77 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 78 79 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 80 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 81 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 82 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 83 84 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 85 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 86 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 87 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 88 89 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000 90 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32 91 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63 92 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000 93 94 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008 95 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0 96 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7 97 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff 98 99 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008 100 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 101 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8 102 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100 103 104 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008 105 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9 106 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9 107 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200 108 109 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 110 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 111 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11 112 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00 113 114 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008 115 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12 116 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12 117 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000 118 119 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 120 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 121 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13 122 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000 123 124 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008 125 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14 126 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14 127 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000 128 129 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 130 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15 131 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15 132 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000 133 134 #define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008 135 #define REO_FLUSH_CACHE_RESERVED_2B_LSB 16 136 #define REO_FLUSH_CACHE_RESERVED_2B_MSB 31 137 #define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000 138 139 #define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 140 #define REO_FLUSH_CACHE_RESERVED_3A_LSB 32 141 #define REO_FLUSH_CACHE_RESERVED_3A_MSB 63 142 #define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000 143 144 #define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 145 #define REO_FLUSH_CACHE_RESERVED_4A_LSB 0 146 #define REO_FLUSH_CACHE_RESERVED_4A_MSB 31 147 #define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff 148 149 #define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 150 #define REO_FLUSH_CACHE_RESERVED_5A_LSB 32 151 #define REO_FLUSH_CACHE_RESERVED_5A_MSB 63 152 #define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000 153 154 #define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 155 #define REO_FLUSH_CACHE_RESERVED_6A_LSB 0 156 #define REO_FLUSH_CACHE_RESERVED_6A_MSB 31 157 #define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff 158 159 #define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 160 #define REO_FLUSH_CACHE_RESERVED_7A_LSB 32 161 #define REO_FLUSH_CACHE_RESERVED_7A_MSB 63 162 #define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000 163 164 #define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 165 #define REO_FLUSH_CACHE_RESERVED_8A_LSB 0 166 #define REO_FLUSH_CACHE_RESERVED_8A_MSB 31 167 #define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff 168 169 #define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 170 #define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32 171 #define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63 172 #define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 173 174 #endif 175