1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _REO_FLUSH_CACHE_STATUS_H_ 23 #define _REO_FLUSH_CACHE_STATUS_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "uniform_reo_status_header.h" 28 #define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 26 29 30 #define NUM_OF_QWORDS_REO_FLUSH_CACHE_STATUS 13 31 32 struct reo_flush_cache_status { 33 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 34 struct uniform_reo_status_header status_header; 35 uint32_t error_detected : 1, 36 block_error_details : 2, 37 reserved_2a : 5, 38 cache_controller_flush_status_hit : 1, 39 cache_controller_flush_status_desc_type : 3, 40 cache_controller_flush_status_client_id : 4, 41 cache_controller_flush_status_error : 2, 42 cache_controller_flush_count : 8, 43 flush_queue_1k_desc : 1, 44 reserved_2b : 5; 45 uint32_t reserved_3a : 32; 46 uint32_t reserved_4a : 32; 47 uint32_t reserved_5a : 32; 48 uint32_t reserved_6a : 32; 49 uint32_t reserved_7a : 32; 50 uint32_t reserved_8a : 32; 51 uint32_t reserved_9a : 32; 52 uint32_t reserved_10a : 32; 53 uint32_t reserved_11a : 32; 54 uint32_t reserved_12a : 32; 55 uint32_t reserved_13a : 32; 56 uint32_t reserved_14a : 32; 57 uint32_t reserved_15a : 32; 58 uint32_t reserved_16a : 32; 59 uint32_t reserved_17a : 32; 60 uint32_t reserved_18a : 32; 61 uint32_t reserved_19a : 32; 62 uint32_t reserved_20a : 32; 63 uint32_t reserved_21a : 32; 64 uint32_t reserved_22a : 32; 65 uint32_t reserved_23a : 32; 66 uint32_t reserved_24a : 32; 67 uint32_t reserved_25a : 28, 68 looping_count : 4; 69 #else 70 struct uniform_reo_status_header status_header; 71 uint32_t reserved_2b : 5, 72 flush_queue_1k_desc : 1, 73 cache_controller_flush_count : 8, 74 cache_controller_flush_status_error : 2, 75 cache_controller_flush_status_client_id : 4, 76 cache_controller_flush_status_desc_type : 3, 77 cache_controller_flush_status_hit : 1, 78 reserved_2a : 5, 79 block_error_details : 2, 80 error_detected : 1; 81 uint32_t reserved_3a : 32; 82 uint32_t reserved_4a : 32; 83 uint32_t reserved_5a : 32; 84 uint32_t reserved_6a : 32; 85 uint32_t reserved_7a : 32; 86 uint32_t reserved_8a : 32; 87 uint32_t reserved_9a : 32; 88 uint32_t reserved_10a : 32; 89 uint32_t reserved_11a : 32; 90 uint32_t reserved_12a : 32; 91 uint32_t reserved_13a : 32; 92 uint32_t reserved_14a : 32; 93 uint32_t reserved_15a : 32; 94 uint32_t reserved_16a : 32; 95 uint32_t reserved_17a : 32; 96 uint32_t reserved_18a : 32; 97 uint32_t reserved_19a : 32; 98 uint32_t reserved_20a : 32; 99 uint32_t reserved_21a : 32; 100 uint32_t reserved_22a : 32; 101 uint32_t reserved_23a : 32; 102 uint32_t reserved_24a : 32; 103 uint32_t looping_count : 4, 104 reserved_25a : 28; 105 #endif 106 }; 107 108 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 109 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 110 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 111 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 112 113 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 114 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 115 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 116 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 117 118 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 119 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 120 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 121 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 122 123 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 124 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 125 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 126 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 127 128 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 129 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 130 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 131 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 132 133 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 134 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0 135 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0 136 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 137 138 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000000000008 139 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1 140 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2 141 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x0000000000000006 142 143 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 144 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3 145 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7 146 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x00000000000000f8 147 148 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000000000008 149 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 150 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8 151 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x0000000000000100 152 153 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000000000008 154 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 155 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11 156 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x0000000000000e00 157 158 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000000000008 159 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 160 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15 161 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x000000000000f000 162 163 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000000000008 164 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 165 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17 166 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x0000000000030000 167 168 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000000000008 169 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 170 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25 171 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x0000000003fc0000 172 173 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 174 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26 175 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26 176 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x0000000004000000 177 178 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000000000008 179 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27 180 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31 181 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0x00000000f8000000 182 183 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 184 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 32 185 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 63 186 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 187 188 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 189 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0 190 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31 191 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 192 193 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 194 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 32 195 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 63 196 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 197 198 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 199 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0 200 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31 201 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 202 203 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 204 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 32 205 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 63 206 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 207 208 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 209 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0 210 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31 211 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 212 213 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 214 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 32 215 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 63 216 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 217 218 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 219 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0 220 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31 221 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 222 223 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 224 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 32 225 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 63 226 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 227 228 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 229 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0 230 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31 231 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 232 233 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 234 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 32 235 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 63 236 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 237 238 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 239 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0 240 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31 241 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 242 243 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 244 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 32 245 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 63 246 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 247 248 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 249 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0 250 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31 251 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 252 253 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 254 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 32 255 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 63 256 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 257 258 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 259 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0 260 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31 261 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 262 263 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 264 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 32 265 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 63 266 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 267 268 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 269 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0 270 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31 271 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 272 273 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 274 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 32 275 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 63 276 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 277 278 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 279 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0 280 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31 281 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 282 283 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 284 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 32 285 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 63 286 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 287 288 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 289 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0 290 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31 291 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 292 293 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 294 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 32 295 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 59 296 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 297 298 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 299 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 60 300 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 63 301 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 302 303 #endif 304