1*5113495bSYour Name 2*5113495bSYour Name /* 3*5113495bSYour Name * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4*5113495bSYour Name * 5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 6*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 7*5113495bSYour Name * above copyright notice and this permission notice appear in all 8*5113495bSYour Name * copies. 9*5113495bSYour Name * 10*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 18*5113495bSYour Name */ 19*5113495bSYour Name 20*5113495bSYour Name 21*5113495bSYour Name 22*5113495bSYour Name #ifndef _REO_FLUSH_QUEUE_H_ 23*5113495bSYour Name #define _REO_FLUSH_QUEUE_H_ 24*5113495bSYour Name #if !defined(__ASSEMBLER__) 25*5113495bSYour Name #endif 26*5113495bSYour Name 27*5113495bSYour Name #include "uniform_reo_cmd_header.h" 28*5113495bSYour Name #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10 29*5113495bSYour Name 30*5113495bSYour Name #define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5 31*5113495bSYour Name 32*5113495bSYour Name struct reo_flush_queue { 33*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 34*5113495bSYour Name struct uniform_reo_cmd_header cmd_header; 35*5113495bSYour Name uint32_t flush_desc_addr_31_0 : 32; 36*5113495bSYour Name uint32_t flush_desc_addr_39_32 : 8, 37*5113495bSYour Name block_desc_addr_usage_after_flush : 1, 38*5113495bSYour Name block_resource_index : 2, 39*5113495bSYour Name reserved_2a : 21; 40*5113495bSYour Name uint32_t reserved_3a : 32; 41*5113495bSYour Name uint32_t reserved_4a : 32; 42*5113495bSYour Name uint32_t reserved_5a : 32; 43*5113495bSYour Name uint32_t reserved_6a : 32; 44*5113495bSYour Name uint32_t reserved_7a : 32; 45*5113495bSYour Name uint32_t reserved_8a : 32; 46*5113495bSYour Name uint32_t tlv64_padding : 32; 47*5113495bSYour Name #else 48*5113495bSYour Name struct uniform_reo_cmd_header cmd_header; 49*5113495bSYour Name uint32_t flush_desc_addr_31_0 : 32; 50*5113495bSYour Name uint32_t reserved_2a : 21, 51*5113495bSYour Name block_resource_index : 2, 52*5113495bSYour Name block_desc_addr_usage_after_flush : 1, 53*5113495bSYour Name flush_desc_addr_39_32 : 8; 54*5113495bSYour Name uint32_t reserved_3a : 32; 55*5113495bSYour Name uint32_t reserved_4a : 32; 56*5113495bSYour Name uint32_t reserved_5a : 32; 57*5113495bSYour Name uint32_t reserved_6a : 32; 58*5113495bSYour Name uint32_t reserved_7a : 32; 59*5113495bSYour Name uint32_t reserved_8a : 32; 60*5113495bSYour Name uint32_t tlv64_padding : 32; 61*5113495bSYour Name #endif 62*5113495bSYour Name }; 63*5113495bSYour Name 64*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 65*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 66*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 67*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 68*5113495bSYour Name 69*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 70*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 71*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 72*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 73*5113495bSYour Name 74*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 75*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 76*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 77*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 78*5113495bSYour Name 79*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x0000000000000000 80*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 32 81*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 63 82*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff00000000 83*5113495bSYour Name 84*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x0000000000000008 85*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0 86*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7 87*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x00000000000000ff 88*5113495bSYour Name 89*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 90*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 91*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8 92*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x0000000000000100 93*5113495bSYour Name 94*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 95*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9 96*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10 97*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000600 98*5113495bSYour Name 99*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x0000000000000008 100*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11 101*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31 102*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0x00000000fffff800 103*5113495bSYour Name 104*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000000000008 105*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_LSB 32 106*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_MSB 63 107*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff00000000 108*5113495bSYour Name 109*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 110*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0 111*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31 112*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0x00000000ffffffff 113*5113495bSYour Name 114*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x0000000000000010 115*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_LSB 32 116*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_MSB 63 117*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff00000000 118*5113495bSYour Name 119*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x0000000000000018 120*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0 121*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31 122*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0x00000000ffffffff 123*5113495bSYour Name 124*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000000000000018 125*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_LSB 32 126*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_MSB 63 127*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff00000000 128*5113495bSYour Name 129*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x0000000000000020 130*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0 131*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31 132*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0x00000000ffffffff 133*5113495bSYour Name 134*5113495bSYour Name #define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 135*5113495bSYour Name #define REO_FLUSH_QUEUE_TLV64_PADDING_LSB 32 136*5113495bSYour Name #define REO_FLUSH_QUEUE_TLV64_PADDING_MSB 63 137*5113495bSYour Name #define REO_FLUSH_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 138*5113495bSYour Name 139*5113495bSYour Name #endif 140