1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _REO_FLUSH_QUEUE_STATUS_H_ 23 #define _REO_FLUSH_QUEUE_STATUS_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "uniform_reo_status_header.h" 28 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 26 29 30 #define NUM_OF_QWORDS_REO_FLUSH_QUEUE_STATUS 13 31 32 struct reo_flush_queue_status { 33 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 34 struct uniform_reo_status_header status_header; 35 uint32_t error_detected : 1, 36 reserved_2a : 31; 37 uint32_t reserved_3a : 32; 38 uint32_t reserved_4a : 32; 39 uint32_t reserved_5a : 32; 40 uint32_t reserved_6a : 32; 41 uint32_t reserved_7a : 32; 42 uint32_t reserved_8a : 32; 43 uint32_t reserved_9a : 32; 44 uint32_t reserved_10a : 32; 45 uint32_t reserved_11a : 32; 46 uint32_t reserved_12a : 32; 47 uint32_t reserved_13a : 32; 48 uint32_t reserved_14a : 32; 49 uint32_t reserved_15a : 32; 50 uint32_t reserved_16a : 32; 51 uint32_t reserved_17a : 32; 52 uint32_t reserved_18a : 32; 53 uint32_t reserved_19a : 32; 54 uint32_t reserved_20a : 32; 55 uint32_t reserved_21a : 32; 56 uint32_t reserved_22a : 32; 57 uint32_t reserved_23a : 32; 58 uint32_t reserved_24a : 32; 59 uint32_t reserved_25a : 28, 60 looping_count : 4; 61 #else 62 struct uniform_reo_status_header status_header; 63 uint32_t reserved_2a : 31, 64 error_detected : 1; 65 uint32_t reserved_3a : 32; 66 uint32_t reserved_4a : 32; 67 uint32_t reserved_5a : 32; 68 uint32_t reserved_6a : 32; 69 uint32_t reserved_7a : 32; 70 uint32_t reserved_8a : 32; 71 uint32_t reserved_9a : 32; 72 uint32_t reserved_10a : 32; 73 uint32_t reserved_11a : 32; 74 uint32_t reserved_12a : 32; 75 uint32_t reserved_13a : 32; 76 uint32_t reserved_14a : 32; 77 uint32_t reserved_15a : 32; 78 uint32_t reserved_16a : 32; 79 uint32_t reserved_17a : 32; 80 uint32_t reserved_18a : 32; 81 uint32_t reserved_19a : 32; 82 uint32_t reserved_20a : 32; 83 uint32_t reserved_21a : 32; 84 uint32_t reserved_22a : 32; 85 uint32_t reserved_23a : 32; 86 uint32_t reserved_24a : 32; 87 uint32_t looping_count : 4, 88 reserved_25a : 28; 89 #endif 90 }; 91 92 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 93 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 94 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 95 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 96 97 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 98 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 99 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 100 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 101 102 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 103 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 104 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 105 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 106 107 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 108 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 109 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 110 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 111 112 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 113 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 114 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 115 #define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 116 117 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 118 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB 0 119 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB 0 120 #define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 121 122 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 123 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB 1 124 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB 31 125 #define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000fffffffe 126 127 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 128 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB 32 129 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB 63 130 #define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 131 132 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 133 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB 0 134 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB 31 135 #define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 136 137 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 138 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB 32 139 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB 63 140 #define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 141 142 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 143 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB 0 144 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB 31 145 #define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 146 147 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 148 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB 32 149 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB 63 150 #define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 151 152 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 153 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB 0 154 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB 31 155 #define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 156 157 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 158 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB 32 159 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB 63 160 #define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 161 162 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 163 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB 0 164 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB 31 165 #define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 166 167 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 168 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB 32 169 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB 63 170 #define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 171 172 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 173 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB 0 174 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB 31 175 #define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 176 177 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 178 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB 32 179 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB 63 180 #define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 181 182 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 183 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB 0 184 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB 31 185 #define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 186 187 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 188 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB 32 189 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB 63 190 #define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 191 192 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 193 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB 0 194 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB 31 195 #define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 196 197 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 198 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB 32 199 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB 63 200 #define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 201 202 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 203 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB 0 204 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB 31 205 #define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 206 207 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 208 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB 32 209 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB 63 210 #define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 211 212 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 213 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB 0 214 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB 31 215 #define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 216 217 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 218 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB 32 219 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB 63 220 #define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 221 222 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 223 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB 0 224 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB 31 225 #define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 226 227 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 228 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB 32 229 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB 63 230 #define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 231 232 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 233 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB 0 234 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB 31 235 #define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 236 237 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 238 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB 32 239 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB 59 240 #define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 241 242 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 243 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB 60 244 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB 63 245 #define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 246 247 #endif 248