1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ 23 #define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "uniform_reo_status_header.h" 28 #define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 26 29 30 #define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 13 31 32 struct reo_flush_timeout_list_status { 33 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 34 struct uniform_reo_status_header status_header; 35 uint32_t error_detected : 1, 36 timout_list_empty : 1, 37 reserved_2a : 30; 38 uint32_t release_desc_count : 16, 39 forward_buf_count : 16; 40 uint32_t reserved_4a : 32; 41 uint32_t reserved_5a : 32; 42 uint32_t reserved_6a : 32; 43 uint32_t reserved_7a : 32; 44 uint32_t reserved_8a : 32; 45 uint32_t reserved_9a : 32; 46 uint32_t reserved_10a : 32; 47 uint32_t reserved_11a : 32; 48 uint32_t reserved_12a : 32; 49 uint32_t reserved_13a : 32; 50 uint32_t reserved_14a : 32; 51 uint32_t reserved_15a : 32; 52 uint32_t reserved_16a : 32; 53 uint32_t reserved_17a : 32; 54 uint32_t reserved_18a : 32; 55 uint32_t reserved_19a : 32; 56 uint32_t reserved_20a : 32; 57 uint32_t reserved_21a : 32; 58 uint32_t reserved_22a : 32; 59 uint32_t reserved_23a : 32; 60 uint32_t reserved_24a : 32; 61 uint32_t reserved_25a : 28, 62 looping_count : 4; 63 #else 64 struct uniform_reo_status_header status_header; 65 uint32_t reserved_2a : 30, 66 timout_list_empty : 1, 67 error_detected : 1; 68 uint32_t forward_buf_count : 16, 69 release_desc_count : 16; 70 uint32_t reserved_4a : 32; 71 uint32_t reserved_5a : 32; 72 uint32_t reserved_6a : 32; 73 uint32_t reserved_7a : 32; 74 uint32_t reserved_8a : 32; 75 uint32_t reserved_9a : 32; 76 uint32_t reserved_10a : 32; 77 uint32_t reserved_11a : 32; 78 uint32_t reserved_12a : 32; 79 uint32_t reserved_13a : 32; 80 uint32_t reserved_14a : 32; 81 uint32_t reserved_15a : 32; 82 uint32_t reserved_16a : 32; 83 uint32_t reserved_17a : 32; 84 uint32_t reserved_18a : 32; 85 uint32_t reserved_19a : 32; 86 uint32_t reserved_20a : 32; 87 uint32_t reserved_21a : 32; 88 uint32_t reserved_22a : 32; 89 uint32_t reserved_23a : 32; 90 uint32_t reserved_24a : 32; 91 uint32_t looping_count : 4, 92 reserved_25a : 28; 93 #endif 94 }; 95 96 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 97 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 98 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 99 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 100 101 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 102 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 103 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 104 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 105 106 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 107 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 108 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 109 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 110 111 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 112 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 113 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 114 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 115 116 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 117 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 118 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 119 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 120 121 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 122 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0 123 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0 124 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 125 126 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000000000008 127 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1 128 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1 129 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x0000000000000002 130 131 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 132 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2 133 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31 134 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0x00000000fffffffc 135 136 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008 137 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 32 138 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 47 139 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff00000000 140 141 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008 142 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 48 143 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 63 144 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff000000000000 145 146 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 147 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0 148 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31 149 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 150 151 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 152 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 32 153 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 63 154 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff00000000 155 156 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 157 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0 158 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31 159 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 160 161 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 162 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 32 163 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 63 164 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff00000000 165 166 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 167 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0 168 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31 169 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 170 171 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 172 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 32 173 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 63 174 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff00000000 175 176 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 177 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0 178 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31 179 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 180 181 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 182 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 32 183 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 63 184 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff00000000 185 186 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 187 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0 188 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31 189 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 190 191 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 192 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 32 193 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 63 194 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff00000000 195 196 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 197 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0 198 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31 199 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 200 201 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 202 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 32 203 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 63 204 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff00000000 205 206 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 207 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0 208 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31 209 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 210 211 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 212 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 32 213 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 63 214 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff00000000 215 216 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 217 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0 218 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31 219 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 220 221 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 222 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 32 223 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 63 224 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff00000000 225 226 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 227 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0 228 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31 229 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 230 231 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 232 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 32 233 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 63 234 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff00000000 235 236 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 237 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0 238 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31 239 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 240 241 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 242 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 32 243 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 63 244 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff00000000 245 246 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 247 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0 248 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31 249 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 250 251 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 252 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 32 253 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 59 254 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 255 256 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 257 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 60 258 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 63 259 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 260 261 #endif 262