1 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _REO_UNBLOCK_CACHE_H_ 23 #define _REO_UNBLOCK_CACHE_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "uniform_reo_cmd_header.h" 28 #define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 10 29 30 #define NUM_OF_QWORDS_REO_UNBLOCK_CACHE 5 31 32 struct reo_unblock_cache { 33 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 34 struct uniform_reo_cmd_header cmd_header; 35 uint32_t unblock_type : 1, 36 cache_block_resource_index : 2, 37 reserved_1a : 29; 38 uint32_t reserved_2a : 32; 39 uint32_t reserved_3a : 32; 40 uint32_t reserved_4a : 32; 41 uint32_t reserved_5a : 32; 42 uint32_t reserved_6a : 32; 43 uint32_t reserved_7a : 32; 44 uint32_t reserved_8a : 32; 45 uint32_t tlv64_padding : 32; 46 #else 47 struct uniform_reo_cmd_header cmd_header; 48 uint32_t reserved_1a : 29, 49 cache_block_resource_index : 2, 50 unblock_type : 1; 51 uint32_t reserved_2a : 32; 52 uint32_t reserved_3a : 32; 53 uint32_t reserved_4a : 32; 54 uint32_t reserved_5a : 32; 55 uint32_t reserved_6a : 32; 56 uint32_t reserved_7a : 32; 57 uint32_t reserved_8a : 32; 58 uint32_t tlv64_padding : 32; 59 #endif 60 }; 61 62 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 63 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 64 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 65 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 66 67 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 68 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 69 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 70 #define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 71 72 #define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 73 #define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 74 #define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 75 #define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 76 77 #define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET 0x0000000000000000 78 #define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB 32 79 #define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB 32 80 #define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK 0x0000000100000000 81 82 #define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000000 83 #define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 33 84 #define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 34 85 #define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000600000000 86 87 #define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET 0x0000000000000000 88 #define REO_UNBLOCK_CACHE_RESERVED_1A_LSB 35 89 #define REO_UNBLOCK_CACHE_RESERVED_1A_MSB 63 90 #define REO_UNBLOCK_CACHE_RESERVED_1A_MASK 0xfffffff800000000 91 92 #define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET 0x0000000000000008 93 #define REO_UNBLOCK_CACHE_RESERVED_2A_LSB 0 94 #define REO_UNBLOCK_CACHE_RESERVED_2A_MSB 31 95 #define REO_UNBLOCK_CACHE_RESERVED_2A_MASK 0x00000000ffffffff 96 97 #define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 98 #define REO_UNBLOCK_CACHE_RESERVED_3A_LSB 32 99 #define REO_UNBLOCK_CACHE_RESERVED_3A_MSB 63 100 #define REO_UNBLOCK_CACHE_RESERVED_3A_MASK 0xffffffff00000000 101 102 #define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 103 #define REO_UNBLOCK_CACHE_RESERVED_4A_LSB 0 104 #define REO_UNBLOCK_CACHE_RESERVED_4A_MSB 31 105 #define REO_UNBLOCK_CACHE_RESERVED_4A_MASK 0x00000000ffffffff 106 107 #define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 108 #define REO_UNBLOCK_CACHE_RESERVED_5A_LSB 32 109 #define REO_UNBLOCK_CACHE_RESERVED_5A_MSB 63 110 #define REO_UNBLOCK_CACHE_RESERVED_5A_MASK 0xffffffff00000000 111 112 #define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 113 #define REO_UNBLOCK_CACHE_RESERVED_6A_LSB 0 114 #define REO_UNBLOCK_CACHE_RESERVED_6A_MSB 31 115 #define REO_UNBLOCK_CACHE_RESERVED_6A_MASK 0x00000000ffffffff 116 117 #define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 118 #define REO_UNBLOCK_CACHE_RESERVED_7A_LSB 32 119 #define REO_UNBLOCK_CACHE_RESERVED_7A_MSB 63 120 #define REO_UNBLOCK_CACHE_RESERVED_7A_MASK 0xffffffff00000000 121 122 #define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 123 #define REO_UNBLOCK_CACHE_RESERVED_8A_LSB 0 124 #define REO_UNBLOCK_CACHE_RESERVED_8A_MSB 31 125 #define REO_UNBLOCK_CACHE_RESERVED_8A_MASK 0x00000000ffffffff 126 127 #define REO_UNBLOCK_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 128 #define REO_UNBLOCK_CACHE_TLV64_PADDING_LSB 32 129 #define REO_UNBLOCK_CACHE_TLV64_PADDING_MSB 63 130 #define REO_UNBLOCK_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 131 132 #endif 133